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CS5530A Datasheet(PDF) 90 Page - Advanced Micro Devices |
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CS5530A Datasheet(HTML) 90 Page - Advanced Micro Devices |
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90 / 259 page  90 AMD Geode™ CS5530A Companion Device Data Book PC/AT Compatibility Logic Revision 1.1 4.5.2 ISA Bus Interface The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write results in two 16-bit ISA transactions or four 8- bit ISA transactions. The ISA controller gathers the data from multiple ISA read cycles and returns TRDY# only after all of the data can be presented to the PCI bus at the same time. SA[23:0] are a concatenation of ISA LA[23:17] and SA[19:0] and perform equivalent functionality at a reduced pin count. Figure 4-8 shows the relationship between a PCI cycle and the corresponding ISA cycle generated. Figure 4-8. Non-Posted PCI-to-ISA Access PCI_CLK ISACLK FRAME# IRDY# TRDY# AD[31:0] (Read) IOR#/IOW# AD[31:0] (Write) BALE STOP# MEMR#/MEMW# |
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