CS5530A datasheet(53/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

PCI Bus Interface

Revision 1.1

4.2.3

Special Bus Cycles–Shutdown/Halt

The PCI interface does not pass Special Bus Cycles to the

ISA interface, since special cycles by definition have no

destination. However, the PCI interface monitors the PCI

bus for Shutdown and Halt Special Bus Cycles.

Upon detection of a Shutdown Special Bus Cycle, a

WM_RST SMI is generated after a delay of three PCI clock

cycles. PCI Shutdown Special Cycles are detected when

C/BE[3:0]# = 0001 during the address phase and AD[31:0]

= xxxx0000h during the data phase. C/BE[3:0]# are also

properly asserted during the data phase.

Upon detection of a Halt Special Bus Cycle, the CS5530A

completes the cycle by asserting TRDY#. PCI Halt Special

Bus Cycles are detected when CBE[3:0]# = 0001 during

the address phase and AD[31:0] = xxxx0001h during the

data phase of a Halt cycle. CBE[3:0]# are also properly

asserted during the data phase.

4.2.4

PCI Bus Parity

When the CS5530A is the PCI initiator, it generates

address parity for read and write cycles. It checks data par-

ity for read cycles and it generates data parity for write

cycles. The PAR signal is an even-parity bit that is calcu-

lated across 36 bits of AD[31:0] plus C/BE[3:0]#.

By default, the CS5530A does not report parity errors.

However, the CS5530A detects parity errors during the

data phase if F0 Index 04h[6] is set to 1. If enabled and a

data parity error is detected, the CS5530A asserts PERR#.

It also asserts SERR# if F0 Index 41h[5] is set to 1. This

allows NMI generation.

The CS5530A also detects parity errors during the address

phase if F0 Index 04h[6] is set. When parity errors are

detected during the address phase, SERR# is asserted

internally. Parity errors are reported to the CPU by enabling

the SERR# source in I/O Port 061h (Port B) control regis-

ter. The CS5530A sets the corresponding error bits in the

PCI Status Register (F0 Index 06h[15:14]). Table 4-5

shows these programming bits.

If the CS5530A is the PCI master for a cycle and detects

PERR# asserted, it generates SERR# internally.

Table 4-5. PERR#/SERR# Associated Register Bits

Bit

Description

F0 Index 04h-05h

PCI Command Register (R/W)

Reset Value = 000Fh

Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when

a parity error is detected. 0 = Disable (Default); 1 = Enable.

F0 Index 06h-07h

PCI Status Register (R/W)

Reset Value = 0280h

Detected Parity Error: This bit is set whenever a parity error is detected.

Write 1 to clear.

Signaled System Error: This bit is set whenever the CS5530A asserts SERR# active.

Write 1 to clear.

F0 Index 41h

PCI Function Control Register 2 (R/W)

Reset Value = 10h

PERR# Signals SERR#: Assert SERR# any time that PERR# is asserted or detected active by the CS5530A (allows

PERR# assertion to be cascaded to NMI (SMI) generation in the system). 0 = Disable; 1 = Enable.

CS5530A Datasheet(PDF) 53 Page - Advanced Micro Devices

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