HD64F2145 datasheet(127/829 Pages) RENESAS

127 / 829 page

Rev. 2.0, 08/02, page 87 of 788

5.2

Input/Output Pins

Table 5.1 summarizes the pins of the interrupt controller.

Table 5.1

Pin Configuration

Symbol

I/O

Function

NMI

Input

Nonmaskable external interrupt

Rising edge or falling edge can be selected

,54: to ,543

Input

Maskable external interrupts

Rising edge, falling edge, or both edges, or level sensing, can

be selected individually for each pin.

.,148 to .,13

Input

Maskable external interrupts

Falling edge or level sensing can be selected.

:8(: to :8(3*

Input

Maskable external interrupts

Falling edge or level sensing can be selected.

Note:* Not supported by the H8S/2148B.

5.3

The interrupt controller has the following registers. For details on the system control register

(SYSCR), refer to section 3.2.2, System Control Register (SYSCR).

• Interrupt control registers A to C (ICRA to ICRC)

• Address break control register (ABRKCR)

• Break address registers A to C (BARA to BARC)

• IRQ sense control registers (ISCRH, ISCRL)

• IRQ enable register (IER)

• IRQ status register (ISR)

• Keyboard matrix interrupt mask registers (KMIMRA, KMIMR)

• Wake-up event interrupt mask register (WUEMRB)

HD64F2145 Datasheet(PDF) 127 Page - Renesas Technology Corp