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HD64F2145 Datasheet(PDF) 131 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 131 Page - Renesas Technology Corp |
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131 / 829 page ![]() Rev. 2.0, 08/02, page 91 of 788 • ISCRL Bit Bit Name Initial Value R/W Description 7 6 IRQ3SCB IRQ3SCA 0 0 R/W R/W 5 4 IRQ2SCB IRQ2SCA 0 0 R/W R/W 3 2 IRQ1SCB IRQ1SCA 0 0 R/W R/W 1 0 IRQ0SCB IRQ0SCA 0 0 R/W R/W IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of ,54Q input 01: Interrupt request generated at falling edge of ,54Q input 10: Interrupt request generated at rising edge of ,54Q input 11: Interrupt request generated at both falling and rising edges of ,54Q input (n = 3 to 0) 5.3.5 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W IRQn Enable (n = 7 to 0) The IRQn interrupt request is enabled when this bit is 1. |
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