HD64F2145 datasheet(128/829 Pages) RENESAS

128 / 829 page

Rev. 2.0, 08/02, page 88 of 788

5.3.1

Interrupt Control Registers A to C (ICRA to ICRC)

The ICR registers set interrupt control levels for interrupts other than NMI and address breaks.

The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2.

Bit

Bit Name

Initial Value

R/W

Description

ICRn7

IRCn0

All 0

R/W

Interrupt Control Level

0: Corresponding interrupt source is interrupt

control level 0 (no priority)

1: Corresponding interrupt source is interrupt

control level 1 (priority)

A to C

Table 5.2

Correspondence between Interrupt Source and ICR

Bit

Bit Name

ICRA

ICRB

ICRC

ICRn7

IRQ0

A/D converter

SCI_0

ICRn6

IRQ1

FRT

SCI_1

ICRn5

IRQ2, IRQ3

—

SCI_2

ICRn4

IRQ4, IRQ5

—

IIC_0

ICRn3

IRQ6, IRQ7

TMR_0

IIC_1

ICRn2

DTC

TMR_1

—

ICRn1

WDT_0

TMR_X , TMR_Y

LPC*

ICRn0

WDT_1

XBS,

Keyboard buffer controller

—

A to C

:

Reserved. The write value should always be 0.

Note:* On products not including LPC, this bit is reserved. The write value should always be 0.

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