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HD64F2145 Datasheet(PDF) 140 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 140 Page - Renesas Technology Corp |
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140 / 829 page ![]() Rev. 2.0, 08/02, page 100 of 788 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program excution state Interrupt generated? NMI An interrupt with interrupt control level 1? IRQ0 IRQ1 IBFI3 IRQ0 IRQ1 IBFI3 I = 0 Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No Yes No Yes No Yes Yes No No Yes Yes No Hold pending Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 |
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