HD64F2145 datasheet(137/829 Pages) RENESAS

137 / 829 page

Rev. 2.0, 08/02, page 97 of 788

An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt

requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and

UI bits in CCR are given priority and processed before interrupt requests from modules that are set

to control level 0 (no priority).

Table 5.3

Interrupt Sources, Vector Addresses, and Interrupt Priorities

Vector Address

Origin of

Interrupt

Source

Name

Vector

Number

Normal

Mode

Advanced

Mode

ICR

Priority

NMI

H'000E

H'00001C

—

High

IRQ0

H'0020

H'000040

ICRA7

IRQ1

H'0022

H'000044

ICRA6

IRQ2

IRQ3

H'0024

H'0026

H'000048

H'00004C

ICRA5

IRQ4

IRQ5

H'0028

H'002A

H'000050

H'000054

ICRA4

External pin

IRQ6, KIN7 to KIN0

IRQ7, KIN15 to KIN8, WUE7 to

WUE0

H'002C

H'002E

H'000058

H'00005C

ICRA3

DTC

SWDTEND (Software activation

data transfer end)

H'0030

H'000060

ICRA2

WDT_0

WOVI0 (Interval timer)

H'0032

H'000064

ICRA1

WDT_1

WOVI1 (Interval timer)

H'0034

H'000068

ICRA0

—

Address break

H'0036

H'00006C

—

A/D

converter

ADI (A/D conversion end)

H'0038

H'000070

ICRB7

—

Reserved for system use

H’003A

H’005E

H’000074

H’0000BC

—

FRT

ICIA (Input capture A)

ICIB (Input capture B)

ICIC (Input capture C)

ICID (Input capture D)

OCIA (Output compare A)

OCIB (Output compare B)

FOVI (Overflow)

Reserved for system use

H'0060

H'0062

H'0064

H'0066

H'0068

H'006A

H'006C

H'006E

H'0000C0

H'0000C4

H'0000C8

H'0000CC

H'0000D0

H'0000D4

H'0000D8

H'0000DC

ICRB6

—

Reserved for system use

H’0070

H’007E

H’0000E0

H’0000FC

—

TMR_0

CMIA0 (Compare match A)

CMIB0 (Compare match A)

OVI0 (Overflow)

Reserved for system use

H'0080

H'0082

H'0084

H'0086

H'000100

H'000104

H'000108

H'00010C

ICRB3

Low

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