HD64F2145 datasheet(142/829 Pages) RENESAS

142 / 829 page

Rev. 2.0, 08/02, page 102 of 788

3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or

when the I bit is set to 1 while the UI bit is cleared to 0.

An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0.

When the I bit is set to 1, only an NMI or address break interrupt request is accepted, and other

interrupts are held pending.

When both the I and UI bits are set to 1, only an NMI or address break interrupt request is

accepted, and other interrupts are held pending.

When the I bit is cleared to 0, the UI bit is not affected.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instruction to be executed after returning from the

interrupt handling routine.

6. The I and UI bits in CCR are set to 1. This masks all interrupts except for an NMI or address

break interrupt.

7. The CPU generates a vector address for the accepted interrupt and starts execution of the

interrupt handling routine at the address indicated by the contents of the vector address in the

vector table.

HD64F2145 Datasheet(PDF) 142 Page - Renesas Technology Corp