HD64F2145 datasheet(160/829 Pages) RENESAS

160 / 829 page

Rev. 2.0, 08/02, page 120 of 788

6.5

Basic Bus Interface

The basic bus interface enables direct connection to ROM and SRAM. For details on selection of

the bus specifications when using the basic bus interface, see table 6.2

6.5.1

Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has

a data alignment function, and controls whether the upper data bus (D15 to D8) or lower data bus

(D7 to D0) is used when the external address space is accessed, according to the bus specifications

for the area being accessed (8-bit access space or 16-bit access space) and the data size.

8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space. With

the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of

data that can be accessed at one time is one byte: a word access is performed as two byte accesses,

and a longword access, as four byte accesses.

D15

D8 D7

Upper data bus

Lower data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

Longword

size

1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)

16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space.

With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are

used for accesses. The amount of data that can be accessed at one time is one byte or one word,

and a longword access is executed as two word accesses.

In byte access, whether the upper or lower data bus is used is determined by whether the address is

even or odd. The upper data bus is used for an even address, and the lower data bus for an odd

address.

HD64F2145 Datasheet(PDF) 160 Page - Renesas Technology Corp