HD64F2145 datasheet(161/829 Pages) RENESAS

161 / 829 page

Rev. 2.0, 08/02, page 121 of 788

D15

D8 D7

Upper data bus

Lower data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

Longword

size

· Even address

Byte size

· Odd address

Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)

6.5.2

Valid Strobes

Table 6.4 shows the data buses used and valid strobes for each access space.

In a read, the

5' signal is valid for both the upper and lower halves of the data bus. In a write, the

+:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half.

Table 6.4

Data Buses Used and Valid Strobes

Area

Access

Size

Read/

Write

Address

Valid

Strobe

Upper Data Bus

(D15 to D8)

Lower Data

Bus (D7 to D0)

Read

—

Ports or others

8-bit

access space

Byte

Write

—

+:5

Valid

Ports or others

Even

Valid

Invalid

Read

Odd

Invalid

Valid

Even

+:5

Valid

Undefined

Byte

Write

Odd

/:5

Undefined

Valid

Read

—

Valid

16-bit

access space

Word

Write

—

+:5, /:5

Valid

Note:* Undefined: Undefined data is output.

Invalid: Input state with the input value ignored.

Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used

as the data bus.

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