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HD64F2145 Datasheet(PDF) 175 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 175 Page - Renesas Technology Corp |
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175 / 829 page  Rev. 2.0, 08/02, page 135 of 788 Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on- chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to addresses H'(FF)EC00 to H'(FF)EFFF in on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. 7.1 Features • Transfer is possible over any number of channels • Three transfer modes Normal, repeat, and block transfer modes are available. • One activation source can trigger a number of data transfers (chain transfer) • Direct specification of 16-Mbyte address space is possible • Activation by software is possible • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC • Module stop mode can be set DTCH80AA_000020020700 |
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