HD64F2145 datasheet(177/829 Pages) RENESAS

177 / 829 page

Rev. 2.0, 08/02, page 137 of 788

7.2.1

DTC Mode Register A (MRA)

MRA selects the DTC operating mode.

Bit

Bit Name

Initial Value

R/W

Description

SM1

SM0

Undefined

—

Source Address Mode 1, 0

These bits specify an SAR operation after a data

transfer.

0X: SAR is fixed

10: SAR is incremented after a transfer

(by +1 when Sz = 0, by +2 when Sz = 1)

11: SAR is decremented after a transfer

(by –1 when Sz = 0, by –2 when Sz = 1)

DM1

DM0

Undefined

—

Destination Address Mode 1, 0

These bits specify a DAR operation after a data

transfer.

0X: DAR is fixed

10: DAR is incremented after a transfer

(by +1 when Sz = 0, by +2 when Sz = 1)

11: DAR is decremented after a transfer

(by –1 when Sz = 0, by –2 when Sz = 1)

MD1

MD0

Undefined

—

DTC Mode

These bits specify the DTC transfer mode.

00: Normal mode

01: Repeat mode

10: Block transfer mode

11: Setting prohibited

DTS

Undefined

—

DTC Transfer Mode Select

Specifies whether the source side or the destination

side is set to be a repeat area or block area in repeat

mode or block transfer mode.

0: Destination side is repeat area or block area

1: Source side is repeat area or block area

Undefined

—

DTC Data Transfer Size

Specifies the size of data to be transferred.

0: Byte-size transfer

1: Word-size transfer

Legend:

Don't care

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