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HD64F2145 Datasheet(PDF) 176 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 176 Page - Renesas Technology Corp |
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176 / 829 page  Rev. 2.0, 08/02, page 136 of 788 Internal address bus Interrupt controller DTC On-chip RAM Internal data bus CPU interrupt request Interrupt request MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERE DTVECR : DTC mode register A, B : DTC transfer count register A, B : DTC source address register : DTC destination register : DTC enable registers A to E : DTC vector register Legend: Figure 7.1 Block Diagram of DTC 7.2 Register Descriptions The DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) • DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to on-chip RAM. • DTC enable registers A to E (DTCERA to DTCERE) • DTC vector register (DTVECR) |
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