HD64F2145 datasheet(190/829 Pages) RENESAS

190 / 829 page

Rev. 2.0, 08/02, page 150 of 788

7.5.7

Number of DTC Execution States

Table 7.5 lists the execution status for a single DTC data transfer, and table 7.6 shows the number

of states required for each execution status.

Table 7.5

DTC Execution Status

Mode

Vector Read

Read/Write

Data Read

Data Write

Internal

Operations

Normal

Repeat

Block transfer

Block size (initial setting of CRAH and CRAL)

Table 7.6

Number of States Required for Each Execution Status

Object to be Accessed

On-Chip

RAM

On-Chip

ROM

On-Chip I/O

Registers

External Devices

Bus width

Access states

Vector read S

—

6 + 2m

3 + m

information

read/write S

1—

—

Byte data read

23 + m

3 + m

Word data read

46 + 2m

3 + m

Byte data write

23 + m

3 + m

Word data

write S

46 + 2m

3 + m

Execution

status

Internal

operation S

The number of execution states is calculated from using the formula below. Note that

Σ is the sum

of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · S

I + Σ (J · SJ + K · SK + L · SL) + M · SM

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