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HD64F2145 Datasheet(PDF) 187 Page - Renesas Technology Corp

Part # HD64F2145
Description  Hitachi 16-Bit Single-Chip Microcomputer
PDF  829 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2145 Datasheet(HTML) 187 Page - Renesas Technology Corp

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Rev. 2.0, 08/02, page 147 of 788
Table 7.4
Register Functions in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Block size counter
DTC transfer count register B
CRB
Transfer counter
Transfer
SAR
or
DAR
DAR
or
SAR
Block area
•
•
•
1st block
N th block
Figure 7.7 Memory Mapping in Block Transfer Mode
7.5.4
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB,
which define data transfers, can be set independently.
Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the
register information start address stored at the DTC vector address, and then reads the first register
information at that start address. After the data transfer, the CHNE bit will be tested. When it has
been set to 1, DTC reads the next register information located in a consecutive area and performs
the data transfer. These sequences are repeated until the CHNE bit is cleared to 0.



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