LTM4677 datasheet(56/110 Pages) AD

56 / 110 page

LTC3888-1

Rev. 0

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In addition, these schemes can easily be mixed and

matched to create any necessary ramping controls, some

of which might prove difficult to implement with conven-

tional analog-only controllers. These programmable fea-

tures greatly simplify system development because rails

can be resequenced without a hardware change as final

product requirements evolve. The LTpowerPlay GUI and

LTC3888-1 onboard EEPROM can be used for this task,

avoiding the need for firmware development to modify

turn on/off relationships between rails. Entire power sys-

tems can easily be scaled up or down, facilitating reuse

of proven hardware macro designs.

VOLTAGE-BASED OUTPUT SEQUENCING

The LTC3888-1 is capable of voltage-based output

sequencing. For concatenated events between members

of the ADI PSM family, it is possible to control one RUN

pin from a GPIO, FAULT or PGOOD pin of a different con-

troller. A hardware configuration of the type shown in

Figure 36 disables the next downstream controller any-

time the upstream output is below the specific UV thresh-

old. If GPIO or FAULT is used, the controlling output must

be configured to only propagate VOUT_UV_UF, and that

IC must have its MFR_GPIO/FAULT_RESPONSE set to

ignore (0x00). Use of the unfiltered VOUT UV fault limit is

recommended because there is less delay between cross-

ing the UV threshold and the GPIO/FAULT pin releasing.

When GPIO/FAULT UV propagation is utilized, an output

deglitching filter can ensure the control does not toggle

repeatedly at lower values of output transition due to

noise on VOUT. If unwanted transitions still occur with

only the internal filter found on most ADI PSM deviced

(typically 250μs), place a capacitor to ground on the out-

put pin. The RC time-constant of the filter should be low

enough to assure no appreciable delay is incurred. A value

of 300μs to 500μs will provide some additional filtering

without significant delay of the trigger event.

When the system is turned off, rails will shut down in the

same order as they turn on, as shown in Figure 37. If a

different sequence is required, the circuit must be rewired

or delays must be added by programming TON_DELAY or

TOFF_DELAY. A fundamental limitation of this application

When the system is turned off, rails will shut down in the

APPLICATIONS INFORMATION

same order as they turn on, as shown in Figure 37. If a

different sequence is required, the circuit must be rewired

or delays must be added by programming TON_DELAY

or TOFF_DELAY. A fundamental limitation of this applica-

tion is the inability of upstream rails to detect a start-up

failure of downstream rails. Due to this, cascade sequenc-

ing should not be implemented without an external fast

supervisor to monitor downstream rails and assert a sys-

tem fault if problems occur.

PWM FREQUENCY SYNCHRONIZATION

The LTC3888-1 incorporates an internal phase-locked

loop (PLL) which enables synchronization of all PWM

channels to an external CMOS clock from 250kHz to

1MHz. The PLL is locked to the falling edge of the SYNC

pin clock signal. For synchronization required by the

application, SYNC may be driven from a separate source,

including another LTC3888-1 or other ADI PSM device.

If SYNC is not externally clocked, the PWMs will operate

at the frequency specified by the FREQUENCY_SWITCH

command.

Figure 36. Cascade Sequencing Configuration Example

Figure 37. Cascade Sequencing Waveforms

LTC3882

GPIO0

GPIO1

RUN 1

RUN 0

START

LTC3888-1

388812 F36

RUN 0

PGOOD0

(PULL-UP RESISTORS

TO 3.3V NOT SHOWN)

PGOOD1

TO NEXT CHANNEL

IN THE SEQUENCE

RUN 1

388812 F37

100ms/DIV

VOUT2

VOUT3

VOUT4

VOUT1

0.5V/DIV

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