LTM4677 datasheet(62/110 Pages) AD

62 / 110 page

LTC3888-1

Rev. 0

For more information www.analog.com

where:

IEXT = total external load drawn from VDD33, including

local pull-up resistors, in amps

IRC25 = total current drawn from VDD25 by LTC3888-1

configuration resistors, in amps

and fPWM is the PWM switching frequency in kHz

The maximum junction temperature of the LTC3888-1 in

°C may then be found from the following equation

TJ = TA + 36 • PD

with ambient temperature TA expressed in °C

DERATING EEPROM RETENTION AT TEMPERATURE

EEPROM read operations between 85°C and 125°C will

not affect data storage. But retention will be degraded if

the EEPROM is written above 85°C or stored or oper-

ated above 125°C. If an occasional fault log is generated

above 85°C, the slight reduction in data retention in the

EEPROM fault log area will not affect the use of the func-

tion or other EEPROM storage. See the Operation section

for other high temperature EEPROM functional details.

Degradation in data retention can be approximated by

calculating the dimensionless acceleration factor using

the following equation.

AF = e

•

TUSE+273

−

TSTRESS+273

⎛

⎝

⎜

⎛

⎝

⎜

⎞

⎠

⎟

⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

Where:

AF = acceleration factor

Ea = activation energy = 1.4eV

k = 8.617 • 10–5 eV/°K

TUSE = is the specified junction temperature

TSTRESS = actual junction temperature in °C

As an example, if the device is stored at 130°C for 10

hours,

TSTRESS = 130°C, and

AF = e

1.4

8.617•10–5

⎛

⎝

⎜

⎞

⎠

⎟ •

398

−

403

⎛

⎝

⎜

⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

= 1.66

indicating the effect is the same as operating the device at

125°C for 10 • 1.66 = 16.6 hours, resulting in a retention

derating of 6.6 hours.

CONFIGURING OPEN-DRAIN PINS

The LTC3888-1 has the following open-drain pins:

• 3.3V Pins

1. PGOOD0/CLKOUT

2. PGOOD1

3. FAULT0, FAULT1

4. SYNC

5. SHARE_CLK

• 5V Capable Pins

(These pins operate correctly when pulled to 3.3V.)

1. RUN0, RUN1

2. ALERT

3. SCL

4. SDA

Most of the above pins have on-chip pull-down transis-

tors that can sink 3mA at 0.4V. The low state threshold

on these pins provides ample noise margin with 3mA of

current. For 3.3V pins, 3mA of current is produced by

a 1.1k pull-up resistor. Unless there are transient speed

issues associated with the RC time constant of the net, a

10k resistor or larger is generally recommended.

The pull-up resistor for PGOOD should be terminated

to the LTC3888-1 VDD33 pin or a separate bias supply

under 3.6V that is up before the LTC3888-1 is enabled.

Otherwise, power-not-good may be falsely indicated after

the PWM outputs are running.

For high speed signals such as SDA and SCL, a lower

value resistor may be required. The RC time constant

should be set to one-third to one-fifth the required rise

time to avoid timing issues. For a 100pF load and a 400kHz

APPLICATIONS INFORMATION

LTM4677 Datasheet(PDF) 62 Page - Analog Devices

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