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LTM4677 Datasheet(PDF) 63 Page - Analog Devices

Part # LTM4677
Description  Dual Loop 8-Phase Step-Down DC/DC Controller with Digital Power System Management
PDF  110 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4677 Datasheet(HTML) 63 Page - Analog Devices

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LTC3888-1
63
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
PMBus communication rate, the resistor pull-up on the
SDA and SCL pins with the time constant set to one-third
the required rise time equals
RPULLUP =
tRISE
3 • 100pF
= 1k
The closest 1% resistor value is 1kΩ. Limit to 1.1kΩ for
best noise margin.
Be careful to minimize parasitic capacitance on the SDA
and SCL lines to avoid communication problems. To esti-
mate the loading capacitance, monitor the signal in ques-
tion and measure how long it takes for the desired signal
to reach approximately 63% of the output value. This is
one time constant.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 500ns when driven by
the LTC3888-1. If the internal oscillator is set for 500kHz
and the load is 100pF with a one-third rise time required,
the resistor calculation is as follows:
RPULLUP =
2µs – 500ns
3 • 100pF
= 5.0k
The closest 1% resistor is 4.99kΩ .
If timing errors are occurring or if the SYNC amplitude is not
as large as required, monitor the waveform and determine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. Otherwise reduce
the pull-up resistor sufficiently to assure proper operation.
Similar results (R < 5kΩ) should be applied to the
PGOOD0 output when configured as CLKOUT to ensure
proper clocking of the slave IC.
The SHARE_CLK output has a nominal period of 10μs
and is pulled low for about 1μs. If the system load on this
shared line is 100pF, the resistor calculation for this line
with a one-third rise time is:
RPULLUP =
9µs
3 • 100pF
= 30k
The closest 1% resistor is 30.1kΩ .
PMBUS COMMUNICATION AND COMMAND
PROCESSING
The LTC3888-1 has a one deep buffer to hold the last data
written for each supported command prior to processing,
as shown in Figure 43. Two distinct parallel sections of the
LTC3888-1 manage command buffering and command
processing to ensure the last data written to any com-
mand is never lost. When the part receives a new com-
mand from the bus, command data buffering copies the
data into the write command data buffer and indicates to
the internal processor that data for that command should
be handled. The internal processor runs in parallel and
performs the sometimes slower task of fetching, convert-
ing (to internal format) and executing commands marked
for processing.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long rela-
tive to PMBus timing. If the part is busy processing a
command, and a new command(s) arrives, execution may
be delayed or processed in a different order than received.
The part indicates when internal calculations are in pro-
cess with bit 5 of MFR_COMMON (Internal Calculations
Not Pending). When the internal processor is busy cal-
culating, bit 5 is cleared. When this bit is set, the part is
ready for another command. An example polling loop is
provided in Figure 44, which ensures that commands are
processed in order while simplifying error handling rou-
tines. MFR_COMMON always returns valid data at PMBus
speeds between 10kHz and 400kHz.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on device configuration and state it
may either NACK the command or return all ones (0xFF)
for reads. It may also generate a BUSY fault and ALERT
notification, or stretch the SCL clock low. For more infor-
mation refer to PMBus Specification V1.2, Part II, Section
10.8.7 and SMBus V2.0 section 4.3.3. Clock stretching
can be enabled by asserting bit 1 of MFR_CONFIG_ALL.
Clock stretching will only occur if enabled and the bus
communication speed exceeds 100kHz.
PMBus protocols for busy devices are well accepted
standards but can make writing system level software



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