LTM4677 datasheet(27/110 Pages) AD

27 / 110 page

LTC3888-1

Rev. 0

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OPERATION

and then back on by the RUN pin or OPERATION com-

mand, including IC reset or power supply cycling.

Hardwired PWM Response to Power Stage UV

Some power stages can also report a undervoltage condi-

tion for their input supplies on the shared TEMP/FAULT bus.

When supported, this condition is indicated by pulling the

bus below any voltage expected for normal operating tem-

perature range. The LTC3888-1 recognizes this UV indica-

tion if enabled by bit 0 of MFR_PWM_MODE_LTC3888-1.

If the power stage does not provide inherent UV indica-

tion on a shared TEMP/FAULT bus, the LTC3888-1 can be

programmed to provide additional power stage undervolt-

age detection by setting bit 5 of MFR_CHAN_CONFIG on

Page 0. Pin 8 is then converted to a VDR_MON input to

monitor the FET gate drive supply voltage (VDR) of the

external power stages for both master channels. Normally

an external resistor divider to set the desired UV threshold

is required. In this case TSNS1 serves as connection for

the shared TEMP/FAULT bus for both master channels

with UV detection disabled, regardless of the state of bit

0 of MFR_PWM_MODE_LTC3888-1 on either page.

When TSNS-based UV detection or VDR_MON are

enabled, power stage UV condition is continuously indi-

cated in bits[15:14] of MFR_PADS_LTC3888-1. If a power

stage UV condition then occurs during PWM operation

or is present when the PWM master is commanded to

start, the master and its associated slave channels are all

latched off. This state is indicated in the LTC3888-1 status

registers and optionally on the ALERT pin. The off condi-

tion is latched until the rail is turned off and then back on

by the RUN pin or OPERATION command, including IC

reset or power supply cycling.

Note that if an enabled power stage UV indication exists

on both master channels that are sequentially turned

on by RUN pin or OPERATION command, the indicated

fault on the first channel on will be cleared if bit 0 of

MFR_CONFIG_ALL is set. However, both channels will be

latched off as described above.

Hardwired PWM Response to VOUT Faults

VOUT undervoltage (UV) and overvoltage (OV) faults

are detected by supervisor comparators. The output

overvoltage comparator guards against transient over-

shoots as well as long term overvoltages at the output.

When an output OV fault is detected, the state is indicated

in the LTC3888-1 status registers and optionally on the

ALERT pin. The master and its associated slave chan-

nels are all commanded off, unless bit 4 of MFR_PWM_

CONFIG_LTC3888-1 is set and bit 4 in the associated

MFR_PWM_MODE_LTC3888-1 command is clear. In that

special case the master phase of the OV rail commands

its power stage to drive low as long as the OV condition

is detected. Regardless, the off condition is latched until

the rail is cycled off and then back on after the fault has

cleared.

UV faults are masked if the channel has been commanded

off or until all of the following criteria are achieved.

• TON_DELAY Has Expired

• The Soft-Start Ramp Has Completed

• TON_MAX_FAULT_LIMIT Has Been Reached

• IOUT_OC_FAULT_LIMIT Has Not Been Reached

• Soft-Off Is Not in Progress

The LTC3888-1 has no hardwired PWM response for out-

put UV faults.

The LTC3888-1 supports optional output UV and OV

warnings that are determined from multiplexed monitor

ADC conversions. The LTC3888-1 has no hardwired PWM

response for output UV or OV warnings.

Power Good Indication

An LTC3888-1 master phase indicates Power Good on its

PGOOD pin and in STATUS_WORD based on selected UV

and OV fault limits. Power Good is indicated as long as

the phase is enabled to run and VOUT is between the UV

and OV fault limits.

Hardwired PWM Response to IOUT Faults

The LTC3888-1 monitors output current as commanded

by the ITH pins, taking into account power stage current

monitor gain, which is provided by PMBus command or

EEPROM values.

LTM4677 Datasheet(PDF) 27 Page - Analog Devices

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