LTM4677 datasheet(23/110 Pages) AD

23 / 110 page

LTC3888-1

Rev. 0

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OPERATION

a controlled turn-off response with defined delay (TOFF_

DELAY) and ramp down rate (VOUT_TRANSITION_RATE).

Finally, each rail can be commanded off by pulling the

associated RUN pin low. Pulling the RUN pin low can force

the master to perform a controlled turn off or immediately

disable all rail power stages, depending on the program-

ming of ON_OFF_CONFIG.

Minimum Output Disable Times

When OPERATION is used to turn off an LTC3888-1 rail,

a minimum output disable time of 120ms is imposed

regardless of how quickly the rail is commanded back

on. If bit 4 of MFR_CHAN_CONFIG is clear, a PMBus com-

mand to turn the channel off also pulses the RUN pin low.

Once the RUN pin is pulled low internally or externally,

a minimum output disable time (RUN forced low by the

LTC3888-1) of TOFF_DELAY + VOUT/VOUT_TRANSITION_

RATE + 136ms is enforced. If MFR_RESTART_DELAY is

greater than this mandatory minimum, the larger value

of MFR_RESTART_DELAY is used. These minimum off

times allow a consistent rail restart with coherent monitor

ADC values and make the LTC3888-1 highly compatible

with other ADI PMBus digital power system management

products.

OUTPUT SHORT CYCLE

An output short cycle condition is created when a master

channel is commanded back on while waiting for con-

trolled turn off to complete based on TOFF_DELAY and

VOUT_TRANSITION_RATE. Any time this occurs, the

LTC3888-1 asserts the short cycle bit in STATUS_MFR_

SPECIFIC. Device response at that point is governed by

bits in MFR_CHAN_CONFIG and SMBALERT_MASK.

Refer to the detailed descriptions of those commands

for additional details. Generally, the LTC3888-1 should be

controlled so that short cycle conditions are not created

during normal operation.

SWITCHING FREQUENCY AND PHASE

There is a high degree of flexibility for setting the PWM

operating frequency of the LTC3888-1. The switching fre-

quency of the PWM can be established with an internal

oscillator or an external time base. The internal phase-

locked loop (PLL) synchronizes PWM control to this tim-

ing reference with proper phase relation. The device can

also be configured to provide the master clock (SYNC)

to other ICs through PMBus command or EEPROM set-

ting. The LTC3888-1 is designated as a clock master by

clearing bit 4 of MFR_CONFIG_ALL. As clock master,

the LTC3888-1 will drive its open-drain SYNC pin at the

selected rate with a pulse width of 500ns. An external

pull-up resistor between SYNC and VDD33 is required in

this case. Only one device connected to SYNC should be

designated to drive the pin. If more than one LTC3888-1

sharing SYNC is programmed as clock master, just one of

the devices is automatically elected to provide the clock.

The others disable their SYNC outputs and indicate this

with bit 10 of MFR_PADS_LTC3888-1.

The LTC3888-1 will automatically accept an external

SYNC input, disabling is own SYNC drive if necessary, as

long as the external clock frequency is greater than one-

half of the programmed internal oscillator. Whether con-

figured to drive SYNC or not, the LTC3888-1 will continue

PWM operation at the selected frequency (FREQUENCY_

SWITCH) using its own internal oscillator if an external

clock signal is subsequently lost.

The MFR_PWM_CONFIG_LTC3888-1 command can be

used to create a specific master/slave configuration and

assign the phase of each channel. Desired master/slave

arrangement can also be set from EEPROM or external

configuration resistors as outlined in Table 11. Phase des-

ignates the relationship between the falling edge of SYNC

and the internal clock edge that sets the PWM latch for

that channel. Additional small propagation delays to the

PWM control pins will apply.

LTM4677 Datasheet(PDF) 23 Page - Analog Devices

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