LTM4677 datasheet(14/110 Pages) AD

14 / 110 page

LTC3888-1

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

RUN0/RUN1 (Pin 20/Pin 21): Run Control Inputs and

Open-Drain Outputs. A voltage above 2V is required on

these pins to enable the respective PWM master chan-

nel. The LTC3888-1 may drive these pins low under cer-

tain reset/restart conditions regardless of any PMBus

command settings. A pullup resistor is required in the

application.

RSET (Pin 22): Resistor Configuration Set Input. Connect

a 1% 18.7kΩ resistor between this pin and GND to set

the selection values for the configuration resistors for

programming bus address, output current limit and other

PWM settings. Refer to the Applications Information sec-

tion for more details.

ASEL0/ASEL1 (Pin 23, Pin 24): Serial Bus Address Select

Inputs. Connect optional 1% resistors between these pins

and GND to select the serial bus interface address. Refer

to the Applications Information section for more detail.

ILIM0_CFG/ILIM1_CFG (Pin 25/Pin 26): Output Current

Limit Configuration Inputs. Connect optional 1% resis-

tors between these pins and GND to select the output

current limit for each channel. Refer to the Applications

Information section for more detail.

PWM_CFG (Pin 27): PWM Configuration Input. Connect

an optional 1% resistor between this pin and GND to con-

figure PWM switching frequency and master/slave con-

figuration. Refer to the Applications Information section

for more detail.

VDD25 (Pin 28): Internal 2.5V Regulator Output. Bypass

this pin to GND with a low ESR 1μF capacitor. Do not load

this pin with external current.

SHARE_CLK (Pin 29): Share Clock Input and Open-

Drain Output. Share clock, nominally 100kHz, is used to

sequence multiple rails in a power system utilizing more

than one ADI PMBus controller. A pull-up resistor to 3.3V

is required in the application. Minimize the capacitance

on this line to ensure the time constant is fast enough for

the application.

VDD33 (Pin 30): Internal 3.3V Regulator Output. Bypass

this pin to GND with a low ESR capacitor (1µF to 2.2µF).

The LTC3888-1 may also be powered from an external

3.3V source attached to this pin for programming pur-

poses only, if the device is otherwise unpowered. Connect

only external passive components for LTC3888-1 configu-

ration and application.

INTVCC (Pin 31): 5.2V Regulator Output. Bypass this pin

to GND with a low ESR 4.7μF capacitor. Connect only

external passive components for LTC3888-1 configura-

tion and application.

VIN (Pin 32): Main Input Supply. Decouple this pin to GND

with a low ESR capacitor (0.1µF to 2.2µF). In applications

where VIN will always operate below 6V, short this pin and

INTVCC together.

IREF (Pin 33): DrMOS Current Sense Reference. This

voltage output provides reference bias for floating current

monitors from DrMOS devices. Decouple this pin to GND

(exposed pad) at the LTC3888-1 and each power stage

with 100nF to 1μF using low ESR capacitors.

GND (Exposed Pad Pin 53): Ground. All small-signal and

compensation components should connect to this pad.

The exposed pad must be soldered to a suitable PCB cop-

per ground plane for proper electrical operation and to

obtain the specified package thermal resistance.

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