LTM4677 datasheet(28/110 Pages) AD

28 / 110 page

LTC3888-1

Rev. 0

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OPERATION

An output overcurrent (OC) fault condition is detected by a

supervisor comparator for each master channel when the

ITH voltage for that channel reaches its maximum allowed

value. Refer to IOUT_OC_FAULT_LIMIT for details. When

an OC fault is detected the controller clamps ITH at the

OC value.

Output OC warnings are determined from multiplexed

monitor ADC conversions. The LTC3888-1 has no hard-

wired PWM response if an output OC warning occurs.

Hardwired PWM Response to Internal Temperature

Faults

An internal temperature sensor measured by the monitor

ADC protects against EEPROM and other IC damage. When

die temperature rises above 130°C, the LTC3888-1 will

NACK any EEPROM-related command except RESTORE_

USER_ALL and MFR_RESET and issue a CML fault for

Invalid/Unsupported Command. Normal EEPROM access

is re-enabled when die temperature drops below 125°C.

Above 160°C, the part shuts down all PWM outputs until

die temperature is below 150°C. Internal temperature fault

limits cannot be adjusted. Writing to the EEPROM above

a die temperature of 85°C is strongly discouraged. Refer

to the Absolute Maximum Ratings for other important

temperature limitations on internal EEPROM use.

External Temperature Faults

The external shared (wire-OR) power stage temperature

bus may also be monitored by the onboard ADC. There

is no hardwired PWM response for sensed external tem-

perature faults or warnings.

Timing Faults

There is no hardwired PWM response to any timing faults.

TON_MAX_FAULT_LIMIT is the time allowed for VOUT

to rise and settle at start-up. The TON_MAX_FAULT_

LIMIT timer, which has a resolution of 10µs, is started

after TON_DELAY has been reached and a soft-start

sequence is started. If the VOUT_UV_FAULT_LIMIT

is not reached or an OC fault remains after the speci-

fied time, fault response is determined by the value of

TON_MAX_FAULT_RESPONSE.

An internal watchdog detects if SHARE_CLK remains low

for more than 64µs. The part then actively holds SHARE_

CLK low for 120ms, ensuring all devices connected to

this shared control observe a minimum RETRY_DELAY

event. The LTC3888-1 sets the SHARE_CLK_LOW bit in

MFR_COMMON to indicate this fault condition.

External Faults

There are no hardware-level responses to any external

faults propagated into the IC through the FAULT pins.

HIGHER-LEVEL FAULT HANDLING

Higher-level input and output fault event handling

(response) can be programmed as described in the fol-

lowing PMBus Command Details section. Once a fault is

detected, several tens of microseconds may be required

for these higher level responses to occur, including related

assertion of a FAULT output. Time filtering programmed in

any specific fault response will be in addition to these nor-

mal processing delays. For many faults, the LTC3888-1

can manage response in one of three ways: ignore, auton-

omous recovery (hiccup), or latch off. The device takes no

additional action beyond previously discussed hardware-

level responses when programmed to ignore a fault.

For autonomous recovery a new soft-start is attempted if

the fault condition is not present after the MFR_RETRY_

DELAY interval has elapsed. MFR_RETRY_DELAY can

be set from 120ms to 83 seconds in 1ms increments.

If the fault persists, the controller will continue to retry

with an interval specified by MFR_RETRY_DELAY. This

avoids damage to external regulator components caused

by repetitive, rapid power cycling.

No retry is attempted for a latch off fault response. In the

latch off state the applicable external power stages are

immediately disabled to stop the transfer of energy to

the load as quickly as possible. The output remains dis-

abled until the master channel is commanded off and then

on, or IC supply power is cycled. Commanding a PWM

channel off and on may require software and/or hardware

intervention depending on its programmed configuration.

LTM4677 Datasheet(PDF) 28 Page - Analog Devices

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