LTM4677 datasheet(26/110 Pages) AD

26 / 110 page

LTC3888-1

Rev. 0

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OPERATION

The ILIM0_CFG and ILIM1_CFG pin settings are described

in application Table 10. These pins select the per-phase

output current limit for each related rail.

PWM_CFG pin settings are described in application

Table 11. This pin selects the master/slave configurnation

and switching frequency of the internal oscillator.

INTERNAL EEPROM WITH CRC

The LTC3888-1 contains internal EEPROM with error cor-

rection code (ECC) to store user configuration settings

and fault log information. EEPROM endurance and reten-

tion for user space and fault log pages are specified in the

Absolute Maximum Ratings and Electrical Characteristics

table.

The integrity of the entire onboard EEPROM is checked

with a CRC calculation each time its data is to be

read, such as after a power-on reset or execution of

RESTORE_USER_ALL. If a CRC error occurs, the CML

bit is set in STATUS_BYTE and STATUS_WORD, the

EEPROM CRC Error bit in STATUS_MFR_SPECIFIC is set,

and the ALERT, SHARE_CLK and RUN pins are pulled low

(PWM channels off). At that point the device will respond

at special address 0x7C, which is activated after an invalid

CRC has been detected. The chip no longer responds at

its specifically assigned address, but will still respond at

global addresses 0x5A and 0x5B. However, use of these

global addresses when attempting to recover from a CRC

issue is not recommended. All power supply rails associ-

ated with a device reporting an invalid CRC should remain

disabled until the issue is resolved.

ADI recommends that the EEPROM not be written when

die temperature is greater than 85°C. If internal die tem-

perature exceeds 130°C, all EEPROM operations except

RESTORE_USER_ALL and MFR_RESET are disabled. Full

EEPROM operation is not re-enabled until die temperature

falls below 125°C. Refer to the Applications Information

section for equations to predict retention degradation due

to elevated operating temperatures.

See the Applications Information section or contact the

factory for details on efficient in-system EEPROM pro-

gramming, including bulk EEPROM programming, which

the LTC3888-1 also supports.

FAULT DETECTION

A variety of fault and warning detection, reporting and

handling mechanisms are provided by the LTC3888-1.

Fault or warning detection capabilities include:

• Input Under/Overvoltage

• Power Stage UV or Fault

• Output Under/Overvoltage

• Output Overcurrent

• External Overtemperature

• Internal Overtemperature

• CML Fault (Communication, Memory, or Logic)

• External Fault Detection via Bidirectional FAULT Pins

Reporting is covered in following sections on status com-

mands (registers) and ALERT pin function. Fault handling

mechanisms include hardwired low level PWM safety

responses that always occur and higher-level program-

mable event management. Both types are covered in the

following sections.

Input Supply Faults

Input undervoltage and overvoltage limits are determined

from multiplexed monitor ADC conversions. Therefore

the input UV/OV response is naturally deglitched by the

typical conversion cycle of the ADC (tens of milliseconds).

There is no hardwired low level PWM response for any

input supply fault.

Hardwired PWM Response to Power Stage Faults

Power stage faults are monitored on the shared TEMP/

FAULT bus attached to an LTC3888-1 TSNS pin. A power

stage fault condition is detected if this bus is pulled above

any voltage expected for normal operating temperature

range. The specific faults that are reported are determined

by the power stage manufacturer. When a power stage

fault is detected, the master and its associated slave chan-

nels are all commanded off. This state is indicated in the

LTC3888-1 status registers and optionally on the ALERT

pin. The off condition is latched until the rail is turned off

LTM4677 Datasheet(PDF) 26 Page - Analog Devices

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