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DSPIC33EP128GS708 Datasheet(PDF) 242 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 242 Page - Microchip Technology |
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242 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 242 2016-2018 Microchip Technology Inc. bit 3 SPITBE: SPIx Transmit Buffer Empty Status bit 1 = SPIxTXB is empty 0 = SPIxTXB is not empty Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Automatically cleared in hardware when SPIxBUF is written, loading SPIxTXB. Enhanced Buffer mode: Indicates TXELM<5:0> = 000000. bit 2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = SPIxTXB is full 0 = SPIxTXB not full Standard Buffer mode: Automatically set in hardware when SPIxBUF is written, loading SPIxTXB. Automatically cleared in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Enhanced Buffer mode: Indicates TXELM<5:0> = 111111. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = SPIxRXB is full 0 = SPIxRXB is not full Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer mode: Indicates RXELM<5:0> = 111111. REGISTER 18-4: SPIxSTATL: SPIx STATUS REGISTER LOW (CONTINUED) Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software. |
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