DSPIC33EP128GS708 datasheet(331/484 Pages) MICROCHIP

331 / 484 page

 2016-2018 Microchip Technology Inc.

DS70005258C-page 331

dsPIC33EPXXXGS70X/80X FAMILY

(m = 0,2,4,6; n = 1,3,5,7)

R/W-0

R-0

R/W-0

TXENn

TXABTn

TXLARBn

TXERRn

TXREQn

RTRENn

TXnPRI1

TXnPRI0

bit 15

bit 8

R/W-0

R-0

R/W-0

TXENm

TXABTm(1) TXLARBm(1) TXERRm(1)

TXREQm

RTRENm

TXmPRI1

TXmPRI0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

See Definition for bits 7-0, controls Buffer n.

bit 7

TXENm: TX/RX Buffer m Selection bit

1 = Buffer, TRBm, is a transmit buffer

0 = Buffer, TRBm, is a receive buffer

bit 6

TXABTm: Message Aborted bit(1)

1 = Message was aborted

0 = Message completed transmission successfully

bit 5

TXLARBm: Message Lost Arbitration bit(1)

1 = Message lost arbitration while being sent

0 = Message did not lose arbitration while being sent

bit 4

TXERRm: Error Detected During Transmission bit(1)

1 = A bus error occurred while the message was being sent

0 = A bus error did not occur while the message was being sent

bit 3

TXREQm: Message Send Request bit

1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent

0 = Clearing the bit to ‘0’ while set requests a message abort

bit 2

RTRENm: Auto-Remote Transmit Enable bit

1 = When a remote transmit is received, TXREQx will be set

0 = When a remote transmit is received, TXREQx will be unaffected

bit 1-0

TXmPRI<1:0>: Message Transmission Priority bits

11 = Highest message priority

10 = High intermediate message priority

01 = Low intermediate message priority

00 = Lowest message priority

Note 1:

This bit is cleared when TXREQmn is set.

Note:

The buffers, SIDx, EIDx, DLCx, Data Field and Receive Status registers, are located in DMA RAM.

DSPIC33EP128GS708 Datasheet(PDF) 331 Page - Microchip Technology

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