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DSPIC33EP128GS708 Datasheet(PDF) 407 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 407 Page - Microchip Technology |
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407 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 407 dsPIC33EPXXXGS70X/80X FAMILY TABLE 30-35: SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS(5) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCKx Input Frequency — — 15 MHz (Note 3) SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge — 6 20 ns SP36 TdoV2scH, TdoV2scL SDOx Data Output Setup to First SCKx Edge 30 — — ns SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 30 — — ns SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns SP50 TssL2scH, TssL2scL SSx to SCKx or SCKx Input 120 — — ns SP51 TssH2doZ SSx to SDOx Output High-Impedance 10 — 50 ns (Note 4) SP52 TscH2ssH TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns (Note 4) SP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 50 ns Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. 5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices with a remappable SCK3 pin. |
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