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DSPIC33EP128GS708 Datasheet(PDF) 421 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 421 Page - Microchip Technology |
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421 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 421 dsPIC33EPXXXGS70X/80X FAMILY TABLE 30-44: SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS(5) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK3 Input Frequency — — 25 MHz (Note 3) SP72 TscF SCK3 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK3 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO3 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO3 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, TscL2doV SDO3 Data Output Valid after SCK3 Edge — 6 20 ns SP36 TdoV2scH, TdoV2scL SDO3 Data Output Setup to First SCK3 Edge 20 — — ns SP40 TdiV2scH, TdiV2scL Setup Time of SDI3 Data Input to SCK3 Edge 20 — — ns SP41 TscH2diL, TscL2diL Hold Time of SDI3 Data Input to SCK3 Edge 15 — — ns SP50 TssL2scH, TssL2scL SS3 to SCK3 or SCK3 Input 120 — — ns SP51 TssH2doZ SS3 to SDO3 Output High-Impedance 10 — 50 ns (Note 4) SP52 TscH2ssH, TscL2ssH SS3 after SCK3 Edge 1.5 TCY + 40 — — ns (Note 4) SP60 TssL2doV SDO3 Data Output Valid after SS3 Edge — — 50 ns Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK3 is 91 ns. Therefore, the SCK3 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI3 pins. 5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin. |
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