AD9161BBCZ datasheet(126/144 Pages) AD

126 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 126 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

CHAR_REPL_DIS

When this input = 1, character

replacement at the end of

frame/multiframe is disabled.

This signal must only be

programmed while the QBD is

held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x0

R/W

[5:4] RESERVED

Reserved.

0x0

SOFTRST

Soft reset. Active high

synchronous reset. Resets all

hardware to power-on state.

0x0

R/W

1 Disables the deframer

reception.

0 Enable deframer logic.

FORCESYNCREQ

Command from application to

assert a sync request (SYNCOUT

). Active high.

0x0

R/W

RESERVED

Reserved.

0x0

REPL_FRM_ENA

When this level input is set, it

enables replacement of frames

received in error. This signal must

only be programmed while the

QBD is held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x1

R/W

0x476 CTRLREG1

[7:5] RESERVED

Reserved.

0x0

QUAL_RDERR

Error reporting behavior for

concurrent NIT and RD errors.

This signal must only be

programmed while the QBD is

held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x1

R/W

0 NIT has no effect on RD error.

1 NIT error masks concurrent RD

error.

DEL_SCR

Alternative descrambler enable.

(see JESD204B Section 5.2.4)

This signal must only be

programmed while the QBD is

held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x0

R/W

1 Descrambling begins at Octet 2

of user data.

0 Descrambling begins at Octet 0

of user data. This is the

common usage.

CGS_SEL

Determines the QBD behavior

after code group sync has been

achieved. This signal must only

be programmed while the QBD

is held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x1

R/W

0 After code group sync is achieved,

the QBD asserts SYNCOUT only if

there are sufficient disparity errors

as per the JESD204B standard.

AD9161BBCZ Datasheet(PDF) 126 Page - Analog Devices

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