AD9161BBCZ datasheet(128/144 Pages) AD

128 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 128 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

0 Simultaneous errors on

multiple lanes are reported as

one error.

1 Detected errors from all lanes

are trapped in a counter and

sequentially signaled on

SYNCOUT.

AR_ECNTR

Automatic reset of error

counter. The error counter that

causes assertion of SYNCOUT is

automatically reset to 0 when

AR_ECNTR = 1. All other

counters are unaffected. This

signal must only be

programmed while the QBD is

held in soft reset

(Register 0x475, Bit 3), and must

not be changed during normal

operation.

0x0

R/W

[2:0] RESERVED

Reserved.

0x0

0x478 KVAL

[7:0] KSYNC

Number of 4 × K multiframes

during ILS. F is the number of

octets per frame. Settings of 1,

2, and 4 are valid. Refer to Table

16 and Table 17. This signal

must only be programmed

while the QBD is held in soft

reset (Register 0x475, Bit 3), and

must not be changed during

normal operation.

0x1

R/W

0x47C ERRORTHRES

[7:0] ETH

Error threshold value. Bad

disparity, NIT disparity, and

unexpected K character errors

are counted and compared to

the error threshold value. When

the count is equal, either an IRQ

is generated or SYNCOUT± is

asserted per the mask register

settings or both. Function is

performed in all lanes. This

signal must only be

programmed while the QBD is

held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0xFF

R/W

0x47D SYNC_ASSERT_MASK

[7:3] RESERVED

Reserved.

0x0

[2:0] SYNC_ASSERT_MASK

SYNCOUT assertion enable

mask for BD, NIT, and UEK error

conditions. Active high,

SYNCOUT assertion enable

mask for BD, NIT, and UEK error

conditions, respectively. When

an error counter, in any lane,

has reached the error threshold

count, ETH[7:0], and the

corresponding SYNC_ASSERT_

MASK bit is set, SYNCOUT is

asserted. The mask bits are as

follows. Note that the bit

sequence is reversed with

respect to the other error count

controls and the error counters.

0x7

R/W

Bit 2 = bad disparity error (BDE).

AD9161BBCZ Datasheet(PDF) 128 Page - Analog Devices

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