AD4697 datasheet(45/107 Pages) AD

45 / 107 page

Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 45 of 107

The AD4697/AD4698 digital interface includes a 4-wire SPI, a

convert start input (CNV), an active low reset input (RESET), and

a BSY_ALT_GP0 pin that functions as a general-purpose pin. The

WLCSP option also includes three additional general-purpose pins

(GP1, GP2, and GP3).

The AD4697/AD4698 digital interface has two operating modes:

mode, the SPI is used to read from and write to the configuration

registers. In conversion mode, the SPI is used to read conversion

results and optional status bits. See the Register Configuration

Mode section and Conversion Mode section for more details on

these operating modes.

The interface logic level is set by the VIO voltage and supports 1.2

V to 1.8 V logic systems. The AD4697/AD4698 use SPI Mode 3

(clock phase (CPHA) = clock polarity (CPOL) = 1).

When in register configuration mode, the digital host can read from

and write to the AD4697/AD4698 configuration registers via the

SPI. The device must be in register configuration mode to perform

the default mode of operation on device power-up and reset.

The register configuration mode protocol is flexible and can be con-

figured for efficient access of large blocks of the configuration regis-

ter map. Each SPI frame consists of at least one instruction phase,

at least one data phase, and an optional 8-bit cyclic redundancy

check (CRC) checksum (see the Checksum Protection section).

Data is transmitted over the SPI MSB first. The format and order of

the instruction and data phases is configurable, as described in the

Instruction Phase section through the Checksum Protection section.

Figure 81 shows an example of a basic SPI frame that consists of

the instruction phase, data phase, and optional CRC checksum.

A CS falling edge starts an SPI frame and a subsequent CS rising

edge ends the SPI frame. Data is latched on the SDI on the SCK

rising edges and shifted out on the SDO on the SCK falling edges.

For all SPI transactions, data is aligned MSB first.

Figure 93 shows a detailed timing diagram for register read and

write operations via the SPI when the device is in register configu-

ration mode. See Table 2 for the timing specifications shown in

Figure 93.

See the Register Details section for a detailed description of the

addresses and functions of the AD4697/AD4698 configuration reg-

isters.

The 5-bit register configuration mode command switches the device

from conversion mode into register configuration mode (see the

Figure 81. Basic SPI Frame

Instruction Phase

Each SPI frame starts with the instruction phase. The instruction

phase immediately follows a CS falling edge (see Figure 81). The

instruction phase consists of a read/write (R/W) bit followed by

a register address word. Set the R/W bit high to initiate a read

instruction or set the R/W bit low to initiate a write instruction.

The register address word specifies the address of the register to

be accessed. The register address word is 15 bits in length (long

addressing) by default, and can be changed to 7 bits in length

(short addressing) with the ADDR_LEN bit in the SPI_CONFIG_B

When using single instruction mode, each register read or write

transaction in an SPI frame begins with an instruction phase.

When using streaming mode, only one instruction phase is required

per SPI frame to access a set of contiguous registers. See the

Single Instruction Mode section and the Streaming Mode section for

instructions on selecting and using these modes.

Data Phase

During the data phase, register data is either shifted out on the

SDO on the SCK falling edges (for register reads) or latched in

on the SDI on the SCK rising edges (for register writes). The data

phase can include the data for an entire register or individual bytes

of the register (see the Multibyte Register Access section).

If the CRC is disabled, the register contents are updated immedi-

ately after the final SCK rising edge of the data phase. If the CRC

is enabled, the register contents are updated immediately after

the final SCK rising edge of the checksum (if the checksum value

matches the data in the data phase).

Address Direction Options

The address direction options control whether the address is set

to automatically increment or decrement when accessing multiple

bytes of data in a single data phase (for example, when accessing

multibyte registers or when streaming mode is enabled). Figure 82

and Figure 83 show SPI frames with both address direction options.

Select between the two address direction options with the

ADDR_DIR bit in the SPI_CONFIG_A register. When the

ADDR_DIR bit is set to 0, the descending address option is select-

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