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CS47L85 Datasheet(PDF) 48 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 48 Page - Cirrus Logic |
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48 / 370 page  CS47L85 48 Rev 4.3 IN1L_PGA_VOL [6:0] IN1L_SRC [1:0] 00 = Differential IN1ALP – IN1ALN 01 = Single-ended IN1ALP (non-inverting) 10 = Differential IN1BP – IN1BN 11 = Single-ended IN1BP (non-inverting) IN1L_ENA ADC IN1ALN/DMICCLK1 IN1ALP IN1L_DMIC_DLY [5:0] IN1R_DMIC_DLY [5:0] IN1L_VOL [7:0] IN1L_MUTE IN1R_VOL [7:0] IN1R_MUTE CLK DAT IN1L_HPF IN1R_HPF IN_HPF_CUT [2:0] IN1_MODE IN1BN IN1BP IN1R_PGA_VOL [6:0] IN1R_SRC [1:0] 00 = Differential IN1RP – IN1RN 01 = Single-ended IN1RP (non-inverting) 10 = Reserved 11 = Reserved ADC IN1RN/DMICDAT1 IN1RP IN1R_ENA IN_VD_RAMP [2:0] IN_VI_RAMP [2:0] IN1_OSR [2:0] IN1_DMIC_SUP [1:0] IN2L_PGA_VOL [6:0] IN2L_SRC [1:0] 00 = Differential IN2ALP – IN2ALN 01 = Single-ended IN2ALP (non-inverting) 10 = Differential IN2BLP – IN2BLN 11 = Single-ended IN2BLP (non-inverting) IN2L_ENA ADC IN2ALN/DMICCLK2 IN2ALP IN2L_DMIC_DLY [5:0] IN2R_DMIC_DLY [5:0] IN2L_VOL [7:0] IN2L_MUTE IN2R_VOL [7:0] IN2R_MUTE CLK DAT IN2L_HPF IN2R_HPF IN2_MODE IN2BLN IN2BLP IN2R_PGA_VOL [6:0] IN2R_SRC [1:0] 00 = Differential IN2ARP – IN2ARN 01 = Single-ended IN2ARP (non-inverting) 10 = Reserved 11 = Single-ended IN2BR (non-inverting) ADC IN2ARN/DMICDAT2 IN2ARP IN2BR IN2R_ENA IN2_OSR [2:0] IN2_DMIC_SUP [1:0] IN3L_PGA_VOL [6:0] IN3L_SRC [1:0] 00 = Differential IN3LP – IN3LN 01 = Single-ended IN3LP (non-inverting) 10 = Reserved 11 = Reserved IN3L_ENA ADC IN3LN/DMICCLK3 IN3LP IN3L_DMIC_DLY [5:0] IN3R_DMIC_DLY [5:0] IN3L_VOL [7:0] IN3L_MUTE IN3R_VOL [7:0] IN3R_MUTE CLK DAT IN3L_HPF IN3R_HPF IN3_MODE IN3R_PGA_VOL [6:0] IN3R_SRC [1:0] 00 = Differential IN3RP – IN3RN 01 = Single-ended IN3RP (non-inverting) 10 = Reserved 11 = Reserved ADC IN3RN/DMICDAT3 IN3RP IN3R_ENA IN3_OSR [2:0] IN3_DMIC_SUP [1:0] Digital Mic Interface Digital Mic Interface Digital Mic Interface Figure 13 Input Signal Paths |
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