CS47L85 datasheet(75/370 Pages) CIRRUS

75 / 370 page

CS47L85

Rev 4.3

DIGITAL CORE OUTPUT MIXERS

The digital core comprises multiple output paths. The output paths associated with AIF1, AIF2, AIF3 and AIF4 are illustrated

in Figure 24. The output paths associated with OUT1, OUT2, OUT3, OUT4, OUT5 and OUT6 are illustrated in Figure 25.

The output paths associated with the SLIMbus interface are illustrated in Figure 26.

A 4-input mixer is associated with each output. The 4 input sources are selectable in each case, and independent volume

control is provided for each path.

The AIF1, AIF2, AIF3 and AIF4 output mixer control registers (see Figure 24) are located at register addresses R1792 (700h)

through to R1967 (7AEh). The OUT1, OUT2, OUT3, OUT4, OUT5 and OUT6 output mixer control registers (see Figure 25)

are located at addresses R1664 (680h) through to R1759 (6DFh). The SLIMbus output mixer control registers (see Figure

26) are located at addresses R1984 (7C0h) through to R2047 (7FFh).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective mixers. Note that the selected input source(s) must be

configured for the same sample rate as the mixer to which they are connected. Sample rate conversion functions are

available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous

Sample Rate Converter (ISRC)

”.

The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled

– SYSCLK must be

present and enabled before selecting other values for these

registers. See “Clocking and Sample Rates” for further details

(including requirements for reconfiguring SYSCLK while digital core mixers are enabled).

The sample rate for the output signal paths is configured using the applicable OUT_RATE, AIFn_RATE or SLIMTXn_RATE

register - see Table 22. Note that sample rate conversion is required when routing the output signal paths to any signal chain

that is asynchronous and/or configured for a different sample rate.

The OUT_RATE, AIFn_RATE or SLIMTXn_RATE registers should not be changed if any of the respective *_SRCn registers

is non-zero. The associated *_SRCn registers should be cleared to 00h before writing new values to OUT_RATE,

AIFn_RATE or SLIMTXn_RATE. A minimum delay of 125us should be allowed between clearing the *_SRCn registers and

writing to the associated OUT_RATE, AIFn_RATE or SLIMTXn_RATE registers. See Table 22 for further details.

The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output mixer

paths. If an attempt is made to enable an output mixer path, and there are insufficient SYSCLK cycles to support it, then the

attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these

circumstances.)

The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

CS47L85 Datasheet(PDF) 75 Page - Cirrus Logic