CS47L85 datasheet(83/370 Pages) CIRRUS

83 / 370 page

CS47L85

Rev 4.3

core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting

other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for

reconfiguring SYSCLK while digital core functions are enabled).

The sample rate for the DRC function is configured using the FX_RATE register - see Table 22. Note that the EQ, DRC and

LHPF functions must all be configured for the same sample rate. Sample rate conversion is required when routing the DRC

signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.

The FX_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated

*_SRCn registers should be cleared to 00h before writing a new value to FX_RATE. A minimum delay of 125us should be

allowed between clearing the *_SRCn registers and writing to the FX_RATE register. See Table 22 for further details.

The DRC functions are enabled using the control registers described in Table 12.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3712

(0E80h)

DRC1_ctrl1

DRC1L_ENA

DRC1 (Left) Enable

0 = Disabled

1 = Enabled

DRC1R_ENA

DRC1 (Right) Enable

0 = Disabled

1 = Enabled

R3720

(0E88h)

DRC2_ctrl1

DRC2L_ENA

DRC2 (Left) Enable

0 = Disabled

1 = Enabled

DRC2R_ENA

DRC2 (Right) Enable

0 = Disabled

1 = Enabled

Table 12 DRC Enable

The following description of the DRC is applicable to each of the DRCs. The associated register control fields are described

in Table 14 and Table 15 for DRC1 and DRC2 respectively.

DRC COMPRESSION / EXPANSION / LIMITING

The DRC supports two different compression regions, separated by a “Knee” at a specific input amplitude. In the region

above the knee, the compression slope DRCn_HI_COMP applies; in the region below the knee, the compression slope

DRCn_LO_COMP applies.

(Note that ‘n’ identifies the applicable DRC 1 or 2.)

The DRC also supports a noise gate region, where low-level input signals are heavily attenuated. This function can be

enabled or disabled according to the application requirements. The DRC response in this region is defined by the expansion

slope DRCn_NG_EXP.

For additional attenuation of signals in the noise gate region, an additional “knee” can be defined (shown as “Knee2” in

Figure 29). When this knee is enabled, this introduces an infinitely steep drop-off in the DRC response pattern between the

DRCn_LO_COMP and DRCn_NG_EXP regions.

The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is near-constant) is illustrated

in Figure 29.

CS47L85 Datasheet(PDF) 83 Page - Cirrus Logic

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