CS47L85 datasheet(98/370 Pages) CIRRUS

98 / 370 page

CS47L85

Rev 4.3

The S/PDIF input control registers (see Figure 32) are located at register addresses R2048 (800h) through to R2057 (809h).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the two S/PDIF channels. Note that the selected input source(s) must

be synchronised to the SYSCLK clocking domain, and configured for the same sample rate as the S/PDIF generator. Sample

rate conversion functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter

(ASRC)

” and “Isochronous Sample Rate Converter (ISRC)”.

The S/PDIF output generator should be kept disabled (SPD1_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for

all digital core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before

selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for

reconfiguring SYSCLK while digital core functions are enabled).

The sample rate of the S/PDIF generator is configured using the SPD1_RATE register - see Table 22. The S/PDIF

transmitter supports sample rates in the range 32kHz up to 192kHz. Note that sample rate conversion is required when

linking the S/PDIF generator to any signal chain that is asynchronous and/or configured for a different sample rate.

The SPD1_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated

*_SRCn registers should be cleared to 00h before writing new values to SPD1_RATE. A minimum delay of 125us should

be allowed between clearing the *_SRCn registers and writing to the SPD1_RATE register. See Table 22 for further details.

The S/PDIF generator is enabled using the SPD1_ENA register bit, as described in Table 17.

The S/PDIF output contains audio data derived from the selected sources. Audio samples up to 24-bit width can be

accommodated. The Validity bits and the Channel Status bits in the S/PDIF data are configured using the corresponding

fields in registers R1474 (5C2h) to R1477 (5C5h).

Refer to S/PDIF specification (IEC 60958-3) for full details of the S/PDIF protocol and configuration parameters.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1474

(05C2h)

SPD1_TX_

Control

SPD1_VAL2

S/PDIF validity (Subframe B)

SPD1_VAL1

S/PDIF validity (Subframe A)

SPD1_ENA

S/PDIF Generator Enable

0 = Disabled

1 = Enabled

R1475

(05C3h)

SPD1_TX_

Channel_St

atus_1

15:8

SPD1_CATCODE [7:0]

00h

S/PDIF Category code

7:6

SPD1_CHSTMODE [1:0]

S/PDIF Channel Status mode

5:3

SPD1_PREEMPH [2:0]

000

S/PDIF Pre-emphasis mode

SPD1_NOCOPY

S/PDIF Copyright status

SPD1_NOAUDIO

S/PDIF Audio / Non-audio indication

SPD1_PRO

S/PDIF Consumer / Professional Mode

R1476

(05C4h)

SPD1_TX_

Channel_St

atus_2

15:12

SPD1_FREQ [3:0]

0000

S/PDIF Indicated sample frequency

11:8

SPD1_CHNUM2 [3:0]

1011

S/PDIF Channel number (Subframe B)

7:4

SPD1_CHNUM1 [3:0]

0000

S/PDIF Channel number (Subframe A)

3:0

SPD1_SRCNUM [3:0]

0001

S/PDIF Source number

R1477

(05C5h)

SPD1_TX_

Channel_St

atus_3

11:8

SPD1_ORGSAMP [3:0]

0000

S/PDIF Original sample frequency

7:5

SPD1_TXWL [2:0]

000

S/PDIF Audio sample word length

SPD1_MAXWL

S/PDIF Maximum audio sample word

length

3:2

SPD1_SC31_30 [1:0]

S/PDIF Channel Status [31:30]

1:0

SPD1_CLKACU [1:0]

Transmitted clock accuracy

Table 17 S/PDIF Output Generator Control

The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the digital mixer

paths. If an attempt is made to enable the SPDIF generator, and there are insufficient SYSCLK cycles to support it, then the

attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these

circumstances.)

The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

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