CS47L85 datasheet(5/370 Pages) CIRRUS

5 / 370 page

CS47L85

Rev 4.3

OUTPUT SIGNAL PATH NOISE GATE CONTROL .................................................................................................................................................... 218

OUTPUT SIGNAL PATH AEC LOOPBACK ................................................................................................................................................................ 220

HEADPHONE OUTPUTS AND MONO MODE ........................................................................................................................................................... 221

SPEAKER OUTPUTS (ANALOGUE) .......................................................................................................................................................................... 222

SPEAKER OUTPUTS (DIGITAL PDM) ....................................................................................................................................................................... 224

EXTERNAL ACCESSORY DETECTION

.......................................................................................................227

JACK DETECT............................................................................................................................................................................................................. 227

JACK POP SUPPRESSION (MICDET CLAMP AND GP SWITCH)............................................................................................................................ 229

CONTROL SEQUENCE FOR JACK DETECT & MICDET CLAMP ............................................................................................................................ 232

MICROPHONE DETECT ............................................................................................................................................................................................. 233

HEADPHONE DETECT ............................................................................................................................................................................................... 238

LOW POWER SLEEP CONFIGURATION

.....................................................................................................243

GENERAL PURPOSE INPUT / OUTPUT

......................................................................................................245

GPIO CONTROL.......................................................................................................................................................................................................... 245

GPIO FUNCTION SELECT.......................................................................................................................................................................................... 247

PIN-SPECIFIC ALTERNATIVE FUNCTION ................................................................................................................................................................ 250

BUTTON DETECT (GPIO INPUT)............................................................................................................................................................................... 251

LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT)................................................................................................................................................ 251

DSP GPIO (LOW LATENCY DSP INPUT/OUTPUT) .................................................................................................................................................. 251

INTERRUPT (IRQ) STATUS OUTPUT........................................................................................................................................................................ 251

FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT ............................................................................................................................................. 252

FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT ........................................................................................................................................... 253

OPCLK AND OPCLK_ASYNC CLOCK OUTPUT ....................................................................................................................................................... 253

PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT ......................................................................................................................................... 254

SPDIF AUDIO OUTPUT .............................................................................................................................................................................................. 254

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT ............................................................................................. 255

OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT....................................................... 255

GENERAL PURPOSE TIMER STATUS OUTPUT ...................................................................................................................................................... 255

EVENT LOGGER FIFO BUFFER STATUS OUTPUT ................................................................................................................................................. 256

GENERAL PURPOSE SWITCH .................................................................................................................................................................................. 256

INTERRUPTS

................................................................................................................................................257

CLOCKING AND SAMPLE RATES

...............................................................................................................287

SYSTEM CLOCKING................................................................................................................................................................................................... 287

SAMPLE RATE CONTROL ......................................................................................................................................................................................... 287

AUTOMATIC SAMPLE RATE DETECTION ................................................................................................................................................................ 288

SYSCLK AND ASYNCCLK CONTROL ....................................................................................................................................................................... 289

DSPCLK CONTROL .................................................................................................................................................................................................... 291

MISCELLANEOUS CLOCK CONTROLS .................................................................................................................................................................... 292

BCLK AND LRCLK CONTROL .................................................................................................................................................................................... 300

CONTROL INTERFACE CLOCKING .......................................................................................................................................................................... 300

FREQUENCY LOCKED LOOP (FLL) .......................................................................................................................................................................... 301

FREE-RUNNING FLL MODE....................................................................................................................................................................................... 313

SPREAD SPECTRUM FLL CONTROL ....................................................................................................................................................................... 314

FLL INTERRUPTS AND GPIO OUTPUT..................................................................................................................................................................... 316

EXAMPLE FLL CALCULATION................................................................................................................................................................................... 316

EXAMPLE FLL SETTINGS .......................................................................................................................................................................................... 317

CONTROL INTERFACE

................................................................................................................................319

4-WIRE (SPI) CONTROL MODE ................................................................................................................................................................................. 320

2-WIRE (I2C) CONTROL MODE ................................................................................................................................................................................. 321

CONTROL WRITE SEQUENCER

.................................................................................................................324

INITIATING A SEQUENCE.......................................................................................................................................................................................... 324

AUTOMATIC SAMPLE RATE DETECTION SEQUENCES ........................................................................................................................................ 328

DRC SIGNAL DETECT SEQUENCES ........................................................................................................................................................................ 329

MICDET CLAMP SEQUENCES .................................................................................................................................................................................. 330

EVENT LOGGER SEQUENCES ................................................................................................................................................................................. 331

BOOT SEQUENCE...................................................................................................................................................................................................... 332

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