VSC8541XMV-05 datasheet(40/101 Pages) MICROCHIP

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Registers

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

4.2.1

Mode Control

The device register at memory address 0 controls several aspects of the VSC8541-02 device

functionality. The following table shows the available bit settings in this register and what they control.

Interrupt status

Reserved

Auxiliary control and status

LED mode select

LED behavior

Extended register page access

Table 21 •

Mode Control, Address 0 (0x00)

Bit Name

Access Description

Default

Software reset

R/W

Self-clearing. Restores all serial management interface (SMI)

registers to default state, except for sticky and super-sticky

bits.

1: Reset asserted.

0: Reset de-asserted. Wait 1 μs after setting this bit to initiate

another SMI register access.

Loopback

R/W

1: Loopback enabled.

0: Loopback disabled. When loopback is enabled, the device

functions at the current speed setting and with the current

duplex mode setting (bits 6, 8, and 13 of this register).

Forced speed selection LSB R/W

Least significant bit. MSB is bit6.

00: 10 Mbps

01: 100 Mbps

10: 1000 Mbps

11: Reserved

Autonegotiation enable

R/W

1: Autonegotiation enabled.

0: Autonegotiation disabled.

Power-down

R/W

1: Power down enabled.

Isolate

R/W

1: Disable MAC interface outputs and ignore MAC interface

inputs.

Restart autonegotiation

R/W

Self-clearing bit.

1: Restart autonegotiation on media interface.

Duplex

R/W

1: Full-duplex.

0: Half-duplex.

Collision test enable

R/W

1: Collision test enabled.

Forced speed selection MSB R/W

Most significant bit. LSB is bit 13.1

00: 10 Mbps

01: 100 Mbps

10: 1000 Mbps

11: Reserved

5:0 Reserved

Reserved.

Table 20 •

Main Registers (continued)

Address Name

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