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VSC8541XMV-05 Datasheet(PDF) 93 Page - Microchip Technology

Part # VSC8541XMV-05
Description  Single Port Gigabit Ethernet Copper PHY with GMII/RGMII/MII/RMII Interfaces
PDF  101 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

VSC8541XMV-05 Datasheet(HTML) 93 Page - Microchip Technology

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Pin Descriptions
VMDS-10513 VSC8541-02 Datasheet Revision 4.1
84
R/GMII
RXD3
25
I/O, PD VDDMAC
GMII/MII/RGMII data output. The logic
state on this pin is latched on the rising
edge of NRESET to configure the device.
See "Hardware Mode Strapping and PHY
Addressing" for details.
R/GMII
RXD4
24
I/O, PD VDDMAC
GMII data output. The logic state on this
pin is latched on the rising edge of
NRESET to configure the device. See
"Hardware Mode Strapping and PHY
Addressing" for details.
R/GMII
RXD5
23
I/O, PD VDDMAC
GMII data output. The logic state on this
pin is latched on the rising edge of
NRESET to configure the device. See
"Hardware Mode Strapping and PHY
Addressing" for details.
R/GMII
RXD6
21
I/O, PD VDDMAC
GMII data output. The logic state on this
pin is latched on the rising edge of
NRESET to configure the device. See
"Hardware Mode Strapping and PHY
Addressing" for details.
R/GMII
RXD7
20
I/O, PD VDDMAC
GMII data output. The logic state on this
pin is latched on the rising edge of
NRESET to configure the device. See
"Hardware Mode Strapping and PHY
Addressing" for details.
R/GMII
TX_EN/TX_CTL
33
I, PD
VDDMAC
GMII/MII transmit data enable input/RGMII
transmit data control input
R/GMII
TX_ER
35
I, PD
VDDMAC
GMII/MII transmit data error input
R/GMII
TXD0
38
I, PD
VDDMAC
GMII/MII/RGMII data input
R/GMII
TXD1
40
I, PD
VDDMAC
GMII/MII/RGMII data input
R/GMII
TXD2
41
I, PD
VDDMAC
GMII/MII/RGMII data input
R/GMII
TXD3
42
I, PD
VDDMAC
GMII/MII/RGMII data input
R/GMII
TXD4
43
I, PD
VDDMAC
GMII data input
R/GMII
TXD5
45
I, PD
VDDMAC
GMII data input
R/GMII
TXD6
46
I, PD
VDDMAC
GMII data input
R/GMII
TXD7
47
I, PD
VDDMAC
GMII data input
SMI
MDC
48
I
VDDMDIO
Management data clock. A 0 MHz to 12.5
MHz reference input is used to clock serial
MDIO data into and out of the PHY.
SMI
MDINT
51
O, OD VDDMDIO
Management interrupt signal. These pins
can be tied together in a wired-OR
configuration with only a single pull-up
resistor.



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