RZSLASHF datasheet(3/65 Pages) RENESAS

3 / 65 page

RZ/Five Group

1. Overview

R01DS0488EJ0110 Rev.1.10

Page 3 of 65

Jun 30, 2025

1.1.2

CPU Peripheral

Item

Description

Clock Pulse Generator

(CPG)

[RZ/Five]

● Generates the clocks from external clock (EXCLK 24 MHz).

Maximum AndesCore™ AX45MP Single core clock: 1.0 GHz

Maximum DDR clock: 666 MHz (DDR3L-1333), 800 MHz (DDR4-1600)

Maximum AXI-bus clock: 200 MHz

Maximum APB-bus clock: 100 MHz

● SSC (Spread Spectrum Clock) supported

Direct Memory Access Controller

(DMAC)

[RZ/Five]

● 2 modules, 16 channels per module

● Transfer request: On-chip peripheral request / auto request (software trigger)

● A specific DMA transfer interval can be specified to adjust the bus occupancy.

● LINK mode (DMA transfer under descriptor control) supported

● Transfer information can be automatically reloaded

Platform-Level Interrupt Controller

(PLIC)

[RZ/Five]

● Andes Platform-Level Interrupt Controller

● 255 priority levels available

● Software-programmable interrupt generation

● External Interrupt pins (NMI, IRQ7 to IRQ0, TINT31-0)

● On-chip peripheral Interrupts: priority level set for each module

General-purpose I/O

(GPIO)

[RZ/Five]

● General-purpose I/O ports

Thermal Sensor Unit

(TSU)

[RZ/Five]

● 1 channel

1.1.3

Internal Memory

Item

Description

System RAM

[RZ/Five]

● RAM of 128 Kbytes (ECC)

RZ/F Datasheet(PDF) 3 Page - Renesas Technology Corp

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