RZSLASHF datasheet(40/65 Pages) RENESAS

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RZ/Five Group

3. Electrical Characteristics

R01DS0488EJ0110 Rev.1.10

Page 40 of 65

Jun 30, 2025

3.5.7

SPI Multi I/O Bus Controller Access Timing

Table 3.34

SPI Multi I/O Bus Contoller Access Timing

1.8 V

3.3 V

(Serial flash connected)

Item

Symbol

Min.

Max.

Min.

Max.

Unit

Figures

Clock cycle

tSPBcyc

15.0

—

15.0

—

Figure 3.24

CLK high pulse width

tSPBWH

0.45

0.55

0.45

0.55

tSPBcyc

Figure 3.24

CLK low pulse width

tSPBWL

0.45

0.55

0.45

0.55

tSPBcyc

Figure 3.24

CLK rise time

tSPBR

—

1.0

—

3.2

Figure 3.24

CLK fall time

tSPBF

—

1.0

—

3.2

Figure 3.24

Data input

setup time

QSPI0_SPCLK base

point (SDR mode

timing adjusted)

tSU

6.7

—

7.5

—

Figure 3.25

QSPI0_SPCLK base

point (DDR mode

timing adjusted)

4.5

—

4.5

—

Figure 3.26

Data input

hold time

QSPI0_SPCLK base

point (SDR mode

timing adjusted)

0.5

—

0.5

—

Figure 3.25

QSPI0_SPCLK base

point (DDR mode

timing adjusted)

1.0

—

1.0

—

Figure 3.26

SSL setup time

tLEAD

1.5 ×

tSPBcyc − 3

8.5 ×

tSPBcyc + 3

1.5 ×

tSPBcyc − 3

8.5 ×

tSPBcyc + 3

Figure 3.25,

Figure 3.26

SSL hold time

tLAG

1 ×

tSPBcyc − 3

8 ×

tSPBcyc + 3

1 ×

tSPBcyc − 3

8 ×

tSPBcyc + 3

Figure 3.25,

Figure 3.26

Continuous transfer delay time

tTD

1 ×

tSPBcyc − 3

8 ×

tSPBcyc + 3

1 ×

tSPBcyc − 3

8 ×

tSPBcyc + 3

Figure 3.25,

Figure 3.26

Data output

delay time

SDR

tOD

―

2.0

―

5.0

Figure 3.25

DDR

―

6.5*2

―

7.5*3

Figure 3.26

Data output

hold time

SDR

tOH

−2.0

―

-5.0

―

Figure 3.25

DDR

1.0*2

―

2.1*3

―

Figure 3.26

Data output

buffer off time

SDR

tBOFF

―

2.0

―

3.0

Figure 3.27

DDR

―

2.0

―

3.0

Figure 3.27

Note 1.

Output load: 15 pF/driving ability: 12 mA

Note 2.

QSPI0_SPCLK frequency: 100 MHz.

Note 3.

QSPI0_SPCLK frequency: 66 MHz

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