RZSLASHF datasheet(2/65 Pages) RENESAS

2 / 65 page

RZ/Five Group

1. Overview

R01DS0488EJ0110 Rev.1.10

Page 2 of 65

Jun 30, 2025

Overview

1.1

Outline of Specification

1.1.1

CPU Core

Item

Description

System CPU AX45MP

[RZ/Five]

● AndesCore™ AX45MP Single core 1.0 GHz

● L1 I-cache 32 Kbytes (Parity) / D-cache 32 Kbytes (ECC)

● ILM 64 Kbytes (ECC) / DLM 64 Kbytes (ECC), Total 128 Kbytes*1

● L2 cache 256 KBytes (ECC)

● Floating point extension DSP/SIMD ISA

● AndeStar™ V5 Instruction Set Architecture (ISA)

Note 1. The ILM and DLM are generally not used in Linux.

Please refer also AndesCoreAX45MP-1C Processor Reference Manual for details.

Boot

[RZ/Five]

● 6 boot modes

Boot Mode 0: Booting from eSD

Boot Mode 1: Booting from eMMC (1.8 V)

Boot Mode 2: Booting from eMMC (3.3 V)

Boot Mode 3: Booting from a serial flash memory (Single / Quad) connected to the SPI Multi

I/O bus space (1.8 V)

Boot Mode 4: Booting from a serial flash memory (Single / Quad) connected to the SPI Multi

I/O bus space (3.3 V)

Boot Mode 5: Booting from SCIF download

Debug Interface

[RZ/Five]

● AndesCore™ AX45MP Debug Subsystem

● JTAG interface supported

● Embedded Debug Module with up to 8 triggers

RZ/F Datasheet(PDF) 2 Page - Renesas Technology Corp