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XM33C321ASPZR Datasheet(PDF) 60 Page - Texas Instruments |
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XM33C321ASPZR Datasheet(HTML) 60 Page - Texas Instruments |
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60 / 122 page ![]() over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tSU.WCLK Word Clock input setup time 10 ns tHOLD:WCLK Word Clock input hold time 1 ns tVALID:ADx Data output valid time VDD ≥ 2.7V, Transmitter mode 18 ns VDD ≥ 1.71V, Transmitter mode 24.5 ns tHOLD:ADx Data output hold time Transmitter mode 3 ns tSU.ADx Data input setup time Receiver mode 6.5 ns tHOLD.ADx Data input hold time Receiver mode 1.5 ns 7.10.6.2 I2S/TDM Timing Diagram tVALID:WCLK tHOLD:WCLK tVALID:ADx tHOLD:ADx tSU:ADx tHOLD:ADx BCLK WCLK Transmit ADx Receive ADx tVALID:WCLK tHOLD:WCLK tVALID:ADx tHOLD:ADx tSU:ADx tHOLD:ADx BCLK WCLK Transmit ADx Receive ADx Controller Mode, SMPL_EDGE = 1 Controller Mode, SMPL_EDGE = 0 Figure 7-7. I2S/TDM Timing Diagram - Controller Mode tSU:WCLK tHOLD:WCLK tVALID:ADx tHOLD:ADx tSU:ADx tHOLD:ADx BCLK WCLK Transmit ADx Receive ADx tSU:WCLK tHOLD:WCLK tVALID:ADx tHOLD:ADx tSU:ADx tHOLD:ADx BCLK WCLK Transmit ADx Receive ADx Target Mode, SMPL_EDGE = 1 Target Mode, SMPL_EDGE = 0 Figure 7-8. I2S/TDM Timing Diagram - Target Mode 7.11 Digital IO over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT Electrical Characteristics VIH High level input voltage All I/O except Reset 0.7*VDD VDD+0.3 V Reset pin 0.85*VDD VDD+0.3 V VIL Low level input voltage All I/O except Reset -0.3 0.3*VDD Reset pin -0.3 0.15*VDD VHYS Hysteresis All I/O except Reset 0.1*VDD Reset pin 0.3*VDD Ilkg High-Z leakage current(2)(3) SDIO 200(4) nA HSIO 200(4) nA HDIO 280(4) nA RPU Pull up resistance 40 kΩ RPD Pull down resistance 40 kΩ MSPM33C321A, MSPM33C3219 SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026 www.ti.com 60 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: MSPM33C321A MSPM33C3219 |
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