XM33C321ASPZR datasheet(73/122 Pages) TI2

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Table 8-5. SRAM Bank Property (continued)

SRAM0

SRAM1/2/3

STANDBY Mode State

RETAINED

OFF

SHUTDOWN Mode State

OFF

For more details, see the SRAM chapter of the MSPM33C3x 160-MHz Microcontrollers Technical Reference

Manual.

8.7 DMA

The direct memory access (DMA) controller allows movement of data from one memory address to another

without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory

to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode,

without having to awaken to move data to or from a peripheral.

The DMA used in these devices is DMA_B and it support the following key features:

• DMA0: 4 independent DMA transfer channels

– Secure resource on reset

– 2 full-feature channel (DMA0-DMA1) supporting repeated transfer modes

– 2 basic channels (DMA2-DMA3) supporting single transfer modes

• DMA1: 12 independent DMA transfer channels

– Non-Secure resource on reset

– 6 full-feature channel (DMA0-DMA5) supporting repeated transfer modes

– 6 basic channels (DMA6-DMA11) supporting single transfer modes

• Configurable DMA channel priorities

• Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer

capability

• Transfer counter block size supports up to 64k transfers of any data type

• Configurable DMA transfer trigger selection

• Active channel interruption to service other channels

• Early interrupt generation for ping-pong buffer architecture

• Cascading channels upon completion of activity on another channel

• Stride mode to support data re-organization, such as 3-phase metering applications

Table 8-6 lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control

bits in the DMA memory mapped registers.

Note

DMA0 has limited access to peripherals in PD0 and can only access PMU (SYSCTL) & UC1 in PD0.

Table 8-6. DMA Trigger Mapping

Trigger 0:41

DMA0

DMA1

Software

Generic Subscriber 0 (FSUB_0)

Generic Subscriber 1 (FSUB_1)

AES Publisher 1

AES Publisher 2

ADC0 SEQ0

ADC0 SEQ1

ADC0 SEQ2

ADC0 SEQ3

ADC1 SEQ0

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MSPM33C321A, MSPM33C3219

SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026

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