M32CSLASH8B datasheet(177/406 Pages) RENESAS

177 / 406 page

Under development

M32C/8B Group

15. Timer A

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 160 of 385

15.1.2.1

Counter Reset by Two-Phase Pulse Signal Processing

The counter value of timer can be set to 0 by a Z-phase pulse signal input (counter reset) when processing

two-phase pulse signals.

This function can be used when all the following conditions are met; timer A3 event counter mode, two-phase

pulse signal processing, free-running count operation type, and multiply-by-4 processing. The Z-phase pulse

signal is applied to the INT2 pin.

When the TAZIE bit in the ONSF register is set to 1 (Z-phase input enabled), Z-phase pulse input is enabled to

reset the counter. To reset the counter by a Z-phase pulse input, set the TA3 register to 0000h beforehand.

A Z-phase pulse input is enabled when the edge of a signal applied to the INT2 pin is detected. The POL bit in

the INT2IC register can determine the edge polarity. The Z-phase pulse must have a pulse width of one or more

timer A3 count source cycles. Figure 15.17 shows relations between two-phase pulses (A-phase and B-phase)

and the Z-phase pulse.

Z-phase pulse input resets the counter in the next count source timing followed a Z-phase pulse input.

A timer A3 interrupt request is generated twice in a row if a timer A3 overflow or underflow, and the counter

reset by an INT2 input occur at the same time. Do not generate a timer A3 interrupt request when this function

is used.

Figure 15.17

Relations between Two-Phase Pulses (A-Phase and B-Phase) and Z-Phase Pulse

Pulse width of one or more count source cycles is required

NOTE:

1. Example when the rising edge of INT2 is selected.

TA3OUT

(A phase)

m + 1

TA3IN

(B phase)

Count source

INT2(1)

(Z phase)

Counter value

M32C/8B Datasheet(PDF) 177 Page - Renesas Technology Corp