M32CSLASH8B datasheet(174/406 Pages) RENESAS

Part #	M32C/8B

Description	RENESAS MCU M16C FAMILY / M32C/80 SERIES

PDF	406 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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174 / 406 page

Under development

M32C/8B Group

15. Timer A

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 157 of 385

Figure 15.15

Operation in Event Counter Mode When Not Handling Two-Phase Pulse Signals

Count starts

FFFFh

Count stops

i = 0 to 4

TAiS bit in the

TABSR register

Contents of the counter

n = contents of the reload

0000h

IR bit in the TAiIC

Input to TAiIN pin

(Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode)

The MR1 bit is set to 1 (rising edges of an external signal counted)

The MR2 bit is set to 0 (UDF register setting)

Bits TCK1 to TCK0 bit are set to 00b (reload)

Underflow

Reload

Overflow

Reload

Set to 0 by an interrupt request acknowledgement or by a program

Decrement to increment

Count resumes

TAiUD bit in the

UDF register

Set to 1 by a program

“H”

“L”

M32C/8B Datasheet(PDF) 174 Page - Renesas Technology Corp