M32CSLASH8B datasheet(176/406 Pages) RENESAS

176 / 406 page

Under development

M32C/8B Group

15. Timer A

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 159 of 385

Figure 15.16

Operation in Event Counter Mode When Handling Two-Phase Pulse Signals on

Timers A2, A3, and A4

Normal processing operation (Timer A2 and timer A3)

Set to 0 by an interrupt request acknowledgement or by a program.

m+1

m+2

m+1

m-1

FFFF

FFFE

FFFF

TAjOUT

TAjIN

<Free-running function>

Counter value

IR bit in the

TAjIC register

m+1

m+2

m+1

m-1

FFFF

m-1

m+1

Counter value

IR bit in the

TAjIC register

Set to 0 by an interrupt request acknowledgement or by a program.

The counter increments at the following timings:

-at the rising edge of TAkIN while TAkOUT is “H”

-at the falling edge of TAkIN while TAkOUT is “L”

-at the rising edge of TAkOUT while TAkIN is “L”

-at the falling edge of TAkOUT while TAkIN is “H”

Set to 0 by an interrupt request acknowledgement or by a program.

m+1

m+2

m+1

m-1

FFFF

FFFE

FFFF

TAkOUT

TAkIN

<Free-running function>

Counter value

IR bit in the

TAkIC register

m+1

m+2

m+1

m-1

FFFF

m-1

m+1

Counter value

IR bit in the

TAkIC register

Set to 0 by an interrupt request acknowledgement or by a program.

: increment

:decrement

The counter decrements at the following timings:

-at the rising edge of TAkIN while TAkOUT is “L”

-at the falling edge of TAkIN while TAkOUT is “H”

-at the rising edge of TAkOUT while TAkIN is “H”

-at the falling edge of TAkOUT while TAkIN is “L”

While an "H" is applied to the TAjOUT pin (j = 2, 3), the counter increments at the rising edge of the TAjIN pin and decrements at

the falling edge.

Multiply-by-4 processing operation (Timer A3 and timer A4)

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