SH7721 datasheet(56/1524 Pages) RENESAS

56 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page lvi of lxii

Table 9.13

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (2)-2..................................................................... 352

Table 9.14

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (3) ........................................................................ 353

Table 9.15

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (4)-1..................................................................... 354

Table 9.15

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (4)-2..................................................................... 355

Table 9.16

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (5)-1..................................................................... 356

Table 9.16

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (5)-2..................................................................... 357

Table 9.17

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (6)-1..................................................................... 358

Table 9.17

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (6)-2..................................................................... 359

Table 9.18

Relationship between Access Size and Number of Bursts.................................... 360

Table 9.19

Access Address in SDRAM Mode Register Write ............................................... 380

Table 9.20

Output Addresses when EMRS Command is Issued ............................................ 383

Table 9.21

Relationship between Bus Width, Access Size, and Number of Bursts................ 386

Section 10 Direct Memory Access Controller (DMAC)

Table 10.1

Pin Configuration.................................................................................................. 409

Table 10.2

Transfer Request Sources ..................................................................................... 423

Table 10.3

Selecting External Request Modes with RS Bits .................................................. 426

Table 10.4

Selecting External Request Detection with DL, DS Bits...................................... 427

Table 10.5

Selecting External Request Detection with DO Bit .............................................. 427

Table 10.6

Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits ..... 429

Table 10.7

Supported DMA Transfers.................................................................................... 434

Table 10.8

Relationship between Request Modes and Bus Modes

by DMA Transfer Category.................................................................................. 441

Section 11 Clock Pulse Generator (CPG)

Table 11.1

Pin Configuration.................................................................................................. 457

Table 11.2

Clock Operating Modes........................................................................................ 458

Table 11.3

Possible Combination of Clock Mode and FRQCR Values ................................. 459

Section 13 Power-Down Modes

Table 13.1

States of Power-Down Modes .............................................................................. 478

Table 13.2

Pin Configuration.................................................................................................. 479

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