SH7721 datasheet(72/1524 Pages) RENESAS

72 / 1524 page

Section 1

Overview

Rev. 3.00

Jan. 18, 2008

Page 10 of 1458

REJ09B0033-0300

1.2

Block Diagram

Super H

CPU core

USB host

controller

(USBH)

LDC

controller

(LCDC)

512-byte

RAM

576-byte

SRAM

128-byte

RAM

256-byte

SRAM

256-byte

SRAM

2.56-kbyte

line buffer

X/Y memory

Instruction/data for

CPU/DSP (16 kbytes)

DSP core

X bus

CPU bus

Internal bus

Peripheral bus

External bus

Internal bus

Y bus

User break

controller (UBC)

Bus state

controller

(BSC)

User debugging

interface (H-UDI)

Analog front end

interface (AFEIF)

MultiMediaCard

interface (MMCIF)

SIM card

interface

(SIM)

PC card

controller

(PCC)

SD host

interface

(SDHI)

Serial I/O

with FIFO

(SIOF0)

Serial I/O

with FIFO

(SIOF1)

USB function controller

1-kbyte FIFO (USBF)

Serial communication

interface 0 with FIFO

128-byte FIFO

(SCIF0/IrDA)

Serial communication

interface 1 with FIFO

128-byte FIFO (SCIF1)

Interrupt

controller

(INTC)

Compare

match

timer (CMT)

A/D

converter

(ADC)

D/A

converter

(DAC)

16-bit

timer pulse

unit (TPU)

Realtime

clock

(RTC)

Clock pulse

generator

(CPG)

Timer unit

(TMU)

Direct memory

access controller

(DMAC)

Peripheral

bus controller

Cache

memory

(32 kbytes)

Cache access

controller (CCN)

Memory

management

unit (MMU)

SSL

accelerator

(SSL)

I2C

Figure 1.1

Block Diagram

1.3

Pin Assignments

1.3.1

Pin Assignments

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