SH7721 datasheet(88/1524 Pages) RENESAS

88 / 1524 page

Section 1

Overview

Rev. 3.00

Jan. 18, 2008

Page 26 of 1458

REJ09B0033-0300

Classification

Symbol

I/O

Name

Function

XTAL

Crystal

For connection to a crystal

resonator.

Clock

CKIO

I/O

System clock

Used as a pin to input external

clock or output clock.

Operating mode

control

MD5 to MD0

Mode set

Sets the operating mode. Do not

change values on these pins

during operation.

MD2 to MD0 set the clock mode,

MD3 and MD4 set the bus width of

area 0 and MD5 sets the endian.

RESETP

Power-on reset

When low, the system enters the

power-on reset state.

RESETM

Manual reset

When low, the system enters the

manual reset state.

STATUS1,

STATUS0

Status output

Indicates the operating state.

BREQ

Bus request

Low when an external device

requests the release of the bus

mastership.

BACK

Bus request

acknowledge

Indicates that the bus mastership

has been released to an external

device. Reception of the

BACK

signal informs the device which

has output the

BREQ signal that it

has acquired the bus.

System control

Chip active

High in normal operation, and low

in hardware standby mode.

NMI

Non-maskable

interrupt

Non-maskable interrupt request

pin. Fix to high level when not in

use.

IRQ5 to IRQ0

Interrupt

requests 5 to 0

Maskable interrupt request pins.

Selectable as level input or edge

input. The rising edge or falling

edge is selectable as the detection

edge. The low level or high level is

selectable as the detection level.

Interrupts

IRL3 to IRL0

Interrupt

requests 3 to 0

Maskable interrupt request pin.

Input a coded interrupt level.

SH7721 Datasheet(PDF) 88 Page - Renesas Technology Corp

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