SH7721 datasheet(66/1524 Pages) RENESAS

66 / 1524 page

Section 1

Overview

Rev. 3.00

Jan. 18, 2008

Page 4 of 1458

REJ09B0033-0300

Item

Features

Direct memory

access controller

(DMAC)

• Number of channels: Six channels (two channels support external requests)

• Address space: 4 Gbytes on architecture

• Data transfer length: Bytes, words (2 bytes), longwords (4 bytes), 16 bytes

(longword

× 4)

• Maximum number of transfer times: 16,777,216 times

• Address mode: Single address mode or dual address mode selectable

• Transfer request: Selectable from external request, on-chip peripheral

module request, and auto request

• Bus mode: Selectable from cycle steal mode (normal mode and intermittent

mode) and burst mode

• Priority: Selectable from channel priority fixed mode and round robin mode

• Interrupt request: Supports interrupt request to CPU at the end of data

transfer

• External request detection: Selectable from DREQ input low/high level

detection and rising/falling detection

• Transfer request acceptance signal: DACK and TEND can be set an active

level

Clock pulse

generator (CPG)

• Clock mode: Input clock selectable from external clock (EXTAL or CKIO)

and crystal resonator

• Generates three types of clocks

 CPU clock: Maximum 133.34 MHz

 Bus clock: Maximum 66.67 MHz

 Peripheral clock: Maximum 33.34 MHz

• Supports power-down mode

 Sleep mode

 Standby mode

 Module standby mode (X/Y memory standby enabled)

• One-channel watchdog timer

Watchdog timer

(WDT)

• One-channel watchdog timer (WDT)

• Interrupt request: WDT only

Timer unit (TMU)

• Internal three-channel 32-bit timer

• Auto-reload type 32-bit down counter

• Internal prescaler for Pφ

• Interrupt request

SH7721 Datasheet(PDF) 66 Page - Renesas Technology Corp

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