SH7721 datasheet(102/1524 Pages) RENESAS

102 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 40 of 1458

REJ09B0033-0300

(5)

P4 Area

The P4 area is defined as a control area which is non-cacheable and non-address translatable. This

area can be accessed only in privileged mode. A part of the LSI’s on-chip I/O is assigned to this

area.

Table 2.1

Virtual Address Space

Address Range Name

Mode

Description

H'00000000 to

H'7FFFFFFF

P0/U0

Privileged/user mode

2-Gbyte physical space, cacheable, address

translatable

In user mode, only this address space can be

accessed.

H'80000000 to

H'9FFFFFFF

Privileged mode

0.5-Gbyte physical space, cacheable

H'A0000000 to

H'BFFFFFFF

Privileged mode

0.5-Gbyte physical space, non-cacheable

H'C0000000 to

H'DFFFFFFF

Privileged mode

0.5-Gbyte physical space, cacheable,

address translatable

H'E0000000 to

H'FFFFFFFF

Privileged mode

0.5-Gbyte control space, non-cacheable

2.2.2

External Memory Space

This LSI uses 29 bits of the 32-bit virtual address to access external memory. In this case, 0.5-

Gbyte of external memory space can be accessed. The external memory space is managed in area

units. Different types of memory can be connected to each area, as shown in figure 2.2. For

details, please refer to section 9, Bus State Controller (BSC).

In addition, area 1 in the external memory space is used as an on-chip I/O space where most of this

LSI’s on-chip I/Os are mapped.

Normally, the upper three bits of the 32-bit virtual address are masked and the lower 29 bits are

used for external memory addresses.*

2 For example, address H'00000100 in the P0 area, address

H'80000100 in the P1 area, address H'A0000100 in the P2 area, and address H'C0000100 in the P3

area of the virtual address space are mapped into address H'00000100 of area 0 in the external

memory space. The P4 area in the virtual address space is not mapped into the external memory

address. If an address in the P4 area is accessed, an external memory cannot be accessed.

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